Elenco delle pubblicazioni di Fabrizio Ferrandi

 

Relativamente alle pubblicazioni svolte in collaborazione con altri autori, l’attività di ricerca è stata svolta in stretta collaborazione tra gli autori, il cui contribuito è pertanto da ritenersi paritetico.

Riviste internazionali con comitato di revisione internazionale

[A1]                M.Bombana, G.Buonanno, P.Cavalloro, F.Ferrandi, D.Sciuto, G.Zaza,
“ALADIN: A Multi-Level Testability Analyzer for VLSI System Design”,
IEEE Transaction on Very Large Scale Integration (VLSI) Systems,
vol. 2, no. 2, June 1994, pp. 157-171.
(versione estesa e rivista di [B1], [B2] e [B3]).

[A2]                F.Ferrandi,
“Reduction of Fault Detection Costs through a BDD Formalism”,
Microprocessing and Microprogramming (The EUROMICRO Journal),
vol. 8 n. 40 Ed. Elsevier Science, 1994, pp. 841-844.
(versione estesa e rivista di [B1], [B2] e [B3]).

[A3]                C.Bolchini, G.Buonanno, F.Ferrandi, D.Sciuto, M.Bombana, P.Cavalloro,
“A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique”,
IEEE - Transaction on Components, Packaging, and Manufacturing Technology Part B; Advanced Packaging,
vol. 18, no. 3, August 1995, pp. 438-447.
(versione estesa e rivista di [B4] e [B5]).

[A4]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Testing Core-Based Digital Systems: A Symbolic Methodology”,
IEEE - Design&Test of Computers,
vol. 14, no. 4, October-December 1997, pp. 69-77.
(versione estesa e rivista di [B7], [B9] e [B10]).

[A5]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Symbolic optimization of interacting controllers based on redundancy identification and removal”,
IEEE - Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 19, no. 7, July 2000, pp. 760-772.
(versione estesa e rivista di [B8]).

[A6]        A. Antola, F. Ferrandi, V. Piuri, M. Sami,
“Semi-Concurrent Error Detection in Data Paths”,
IEEE - Transactions on Computers,
vol. 50, no. 5, May 2001, pp. 449-465.

[A7]        R. Cordone, F.Ferrandi, D. Sciuto, R. Wolfler Calvo,
“An Efficient Heuristic Approach to Solve the Unate Covering Problem”
accettato per la pubblicazione su Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 20, n. 12, December 2001.
(versione estesa e rivista di [B32]).

[A8]                F.Ferrandi, F.Fummi, D.Sciuto,
“Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications”
accettato per la pubblicazione su Transactions on Computers special issue on embedded fault-tolerant computer systems.
(versione estesa e rivista di [B28], [B33])

[A9]        G. Biasoli, F.Ferrandi, A. Fin, F.Fummi, D.Sciuto
“Behavioral Test Generation for the Selection of BIST Logic”
accettato per la pubblicazione su Journal of System Architecture, JSA.
(versione estesa e rivista di [B35]).

Conferenze internazionali con comitato di revisione internazionale

[B1]                M.Bombana, G.Buonanno, P.Cavalloro, F.Ferrandi, D.Sciuto, G.Zaza,
“An Expert Solution to Functional Testability Analysis of VLSI Circuits”,
Proc. SEKE 93 – 5th International Conference on Software Engineering and Knowledge Engineering,
San Francisco, California, USA, June 16-18 1993, pp. 263-265.

[B2]                M.Bombana, G.Buonanno, P.Cavalloro, F.Ferrandi, D.Sciuto, G.Zaza,
“Reduction of Fault Detection Cost through Testable Design of Sequential Architectures with Signal Feedbacks”,
Proc. IEEE DFT 93 – IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems,
Venice, Italy, October 27-29 1993, pp. 223-230.

[B3]                M.Bombana, G.Buonanno, P.Cavalloro, F.Ferrandi, D.Sciuto, G.Zaza,
“Cycles Analysis for Testability of WSI Sequential Architectures”,
Proc. IEEE WSI 94 – 6th IEEE International Conference on Wafer Scale Integration,
San Francisco, California, USA, January 19-21 1994, pp.188-197.

[B4]         D.Sciuto, C.Bolchini, G.Buonanno, F.Ferrandi, M.Bombana, P.Cavalloro, G.Zaza
“Towards WSI Testable Devices: an Improved Scan Insertion Technique”
Proc. IEEE WSI 95 – 7th IEEE International Conference on Wafer Scale Integration,
San Francisco, California, USA, January 18-20 1995, pp. 339-348.

[B5]                C.Bolchini, G.Buonanno, F.Ferrandi, D.Sciuto, M.Bombana, P.Cavalloro,
“Assessment of functional testability properties from VHDL descriptions”
Proc. VHDL-FORUM EUROPE Spring ‘95 - Working Conference,
Nantes, France, April 24-25 1995, pp. 84-95.

[B6]                G.Buonanno, F.Ferrandi, D.Sciuto,
“Data-Path Efficient Testability Analysis Based on BDDs”,
Proc. IEEE ISCAS '95 – IEEE International Symposium on Circuits and Systems,
Seattle, Washington, USA, April 29 - May 3 1995, pp. 2012-2015.

[B7]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Test Generation for Networks of Interacting FSMs Using Symbolic Techniques”,
Proc. IEEE GLS-VLSI '96 – The 6th Great Lake Symposium on VLSI,
Ames, Iowa, USA, March 22-23 1996, pp. 208-213.

[B8]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques”,
Proc. ACM/IEEE DAC – 33rd ACM/IEEE Design Automation Conference,
Las Vegas, Nevada, USA, June 3-7 1996, pp. 467-470.

[B9]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“BDD-Based Testability Estimation of VHDL Designs”,
Proc. IEEE EURO-DAC '96 – European Design Automation Conference and EURO-VHDL,
Geneva, Switzerland, Sept. 16-20 1996, pp. 444-449.
Best Paper Award EURO-VHDL '96.

[B10]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Simplifying Sequential Gate-Level Test Generation Through Exploitation of High-Level Information”,
Proc. ETW '96 – IEEE European Test Workshop,
Sete Montpellier, France, June 12-14, 1996, pp. 154-158.

[B11]                F.Ferrandi, F.Fummi, R.Bevacqua, L.Guerrazzi,
“Implicit Test Sequences Compaction for Decreasing Test Application Cost”,
Proc. IEEE ICCD '96 – IEEE International Conference on Computer Design: VLSI in Computers, and Processors,
Austin, Texas, USA, Oct. 7-9 1996, pp. 384-389.

[B12]                F.Ferrandi, F.Fummi, R.Bevacqua, L.Guerrazzi,
“Sequential Test Compaction for Test Embedding”,
Proc. OLTW '96 – 2nd IEEE International On-Line Testing Workshop,
San-Jean De-Luz Biarritz, France, July 8-10 1996, pp. 229-230.

[B13]                G.Buonanno, F.Ferrandi, D.Sciuto,
“Testability Analysis of Pipelined Data Path”,
Proc. IEEE ISIS '96 – IEEE International Conference on Innovative System in Silicon,
Austin, Texas, U.S.A, October 9-11, 1996, pp. 259-268.

[B14]                M.Bombana, P.Cavalloro, F.Ferrandi,
“Good Practice for Property Verification in the design of Telecom Applications”,
Proc. ACM/IEEE ASP-DAC '97 – ACM/IEEE Asia and South Pacific Design Automation Conference,
Chiba, Japan, January 28-31 1997, pp. 167-172.

[B15]                G.Buonanno, F.Ferrandi, L.Ferrandi, F.Fummi, D.Sciuto,
“How an “Evolving” Fault Model Improves the Behavioral Test Generation”,
Proc. IEEE GLS-VLSI '97 – The 7th Great Lake Symposium on VLSI,
Ames, Iowa, USA, March 22-23 1997, pp.124-129.

[B16]       A.Allara, M.Bombana, P.Cavalloro, F.Ferrandi,
“Requirements and experiences for formal design of telecom systems”,
Proc. Workshop on Formal Design of Safety Critical Embedded Systems,
Munich, Germany, April 16-18 1997.

[B17]                G.Buonanno, F.Ferrandi, F.Fummi, D.Sciuto, P.Cavalloro,
“An Extended Testing Methodology for VHDL Based High-Level Design”,
Proc. VHDL Forum for CAD in Europe,
Toledo, Spain, April 20-25 1997, pp. 63-74.

[B18]       M.Bacis, G.Buonanno, F.Ferrandi, F.Fummi, L.Gerli, D.Sciuto,
“Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels”,
Proc. IEEE ICCD '97 – IEEE International Conference on Computer Design: VLSI in Computers and Processors,
Austin, Texas, 13-15 October, 1997, pp. 654-659.

[B19]                F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto,
“Power Estimation of Behavioral VHDL Descriptions”,
Proc. IEEE DATE ’98 – Design, Automation and Test in Europe,
Paris, France, February 24-26, 1998, pp. 762-766.

[B20]                F.Ferrandi, F.Fummi, L.Pozzi, M.Sami,
“Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays”,
Proc. IEEE DFT 97 – IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,
Paris, France, October 20-22, 1997, pp. 85-93.

[B21]                F.S.Bietti, F.Ferrandi, F.Fummi, D.Sciuto,
“VHDL Testability Analysis based on Faults Clustering and Implicit Faults Injection”,
Proc. IEEE GLS-VLSI '98 – The 8th Great Lakes Symposium on VLSI,
Lafayette, Louisiana, 19-21 February, 1998, pp. 237-242.

[B22]                F.Ferrandi, A.Macii, E.Macii, M.Poncino, R.Scarsi, F.Somenzi,
“Layout-oriented Synthesis of PTL Circuits based on BDDs”,
Proc. IWLS’98 – 1998 IEEE/ACM International Workshop on Logic Synthesis,
Lake Tahoe, California, 7-10 June , 1998.

[B23]                M.Bombana, P.Cavalloro, F.Ferrandi, F.Fummi, D.Sciuto,
“Implicit Testability Techniques for VHDL Based ASIC Design”,
Proc. ETW’98 – IEEE European Test Workshop,
Barcelona, Spain, May 27-29, 1998, pp. 133-134.

[B24]                F.Ferrandi, F.Fummi, D.Sciuto,
“Behavioral Test Generation for Test Embedding”,
Proc. IOLTW '98 – 4th IEEE Int. On-Line Testing Workshop,
Capri, Italy, July 6-8, 1998, pp. 100-104.

[B25]                D.Corvino, I.Epicoco, F.Ferrandi, F.Fummi, D.Sciuto,
“Controller and Data-Path Separation by VHDL Restructuring”,
Proc. Forum on Design Languages – FDL’98: VHDL Users’ Forum in Europe (VUFE),
Lausanne, Switzerland, Sept. 7-11 1998, pp. 237-243.

[B26]                M.Bombana, P.Cavalloro, F.Ferrandi, F.Fummi, D.Sciuto,
“The REQUEST Testability methodology for VHDL based ASIC design”,
Proc. Forum on Design Languages – FDL’98: VHDL Users’ Forum in Europe (VUFE),
Lausanne, Switzerland, Sept. 7-11 1998, pp. 209-215.

[B27]                D.Corvino, I.Epicoco, F.Ferrandi, F.Fummi, D.Sciuto,
“Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement”,
Proc. IEEE ICCD '98 – IEEE International Conference on Computer Design: VLSI in Computers and Processors,
Austin, Texas, USA, Oct. 5-7 1998, pp. 436-441.

[B28]                F.Ferrandi, F.Fummi, D.Sciuto,
“Implicit Test Generation for Behavioral VHDL Models”,
Proc. IEEE ITC’98 – IEEE International Test Conference,
Washington, D.C., USA, Oct. 18-23, 1998, pp. 587-596.

[B29]                F.Ferrandi, A.Macii, E.Macii, M.Poncino, R.Scarsi, F.Somenzi,
“Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits Symbolic Algorithms for Layout-Oriented PTL Synthesis”,
Proc. ACM/IEEE ICCAD’98 –  ACM/IEEE International Conference on Computer-Aided Design,
San Jose, CA, November 8 - 12, 1998, pp. 235 -241.

[B30]                F.Ferrandi, F.Fummi, L.Gerli, D.Sciuto,
“Symbolic functional vector generation for VHDL specifications”
Proc. IEEE DATE ’99 – Design, Automation and Test in Europe,
Munich, Germany, March 9-12,1999, pp.  442-446.
Best Paper Award DATE '99.

[B31]       M.Brera, F.Ferrandi, D.Sciuto, F. Fummi,
“Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information”,
Proc. IEEE DFT 99 –  IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,
Albuquerque, New Mexico, November 1-3, 1999, pp. 174-180.

[B32]       R. Cordone, F.Ferrandi, D. Sciuto, R. Wolfler Calvo,
“An Efficient Heuristic Approach to Solve the Unate Covering Problem”
Proc. IEEE DATE 2000 – Design, Automation and Test in Europe,
Paris, Franch, March 27 - 30, 2000, pp. 364-371.

[B33]       F. Ferrandi, G. Ferrara, G. Fornara, F. Fummi, D. Sciuto,
“Testability Alternatives Exploration through Functional Testing”,
Proc. IEEE VTS 2000 – 18th IEEE VLSI Test Symposium,
Montreal, Canada, April 30- May 4, 2000, pp. 124-129.

[B34]       F. Ferrandi, A.Fin, F.Fummi, D.Sciuto,
“An Application of Genetic Algorithms and BDDs to Functional Testing”,
Proc. IEEE ICCD’00 – IEEE International Conference on Computer Design: VLSI in Computers and Processors,
Austin, Texas, September 17-20, 2000, pp.48-56.

[B35]       G. Biasoli, F. Ferrandi, A.Fin, F.Fummi, D.Sciuto,
“BIST Architectures Selection Based on Behavioral Testing”,
Proc. IEEE DFT’00 – IEEE International Symposium on Defect and Fault Tollerance in VLSI Systems,
Yamanashi, Japan, October 25-27, 2000, pp. 292-298.

[B36]       M. Beardo, F. Bruschi, F. Ferrandi, D. Sciuto,
“An Approach to Functional Testing of VLIW Architectures”,
Proc. IEEE HLDVT'00 – 5th IEEE International Workshop on High Level Design Validation and Test,
Berkeley, California, USA, November 8-10, 2000, pp. 29-33.

[B37]       F. Ferrandi, G. Ferrara, D. Sciuto, A. Fin, F. Fummi,
“Functional Test Generation for Behaviorally Sequential Models”,
Proc. IEEE DATE 2001 – Design, Automation and Test in Europe,
Munich, Germany, March 13-16, 2001, pp. 403-410.

[B38]       A. Allara, M. Bombana, P. Cavalloro F. Ferrandi,
“Requirements for synthesis-oriented modeling in SystemC”,
Proc. FDL’01 – Forum on Design Lsanguages,
Lyon, France, September 3-7, 2001.

[B39]       F. Ferrandi, M. Rendine, D. Sciuto,
“Functional verification for SystemC descriptions using constraint solving”,
accettato per la pubblicazione su Proc. IEEE DATE 2002 – Design, Automation and Test in Europe,
Paris, France, March 4-8, 2002.

[B40]       F. Bruschi, M. Chiamenti, F. Ferrandi, D. Sciuto,
“Error simulation based on the SystemC design description language”,
accettato per la pubblicazione su Proc. IEEE DATE 2002 – Design, Automation and Test in Europe,
Paris, France, March 4-8, 2002.

[B41]       M. Bombana, F. Bruschi, F. Ferrandi, D. Sciuto,
“SystemC Specification of a Telecom PCI-compatible Interface”,
accettato per la pubblicazione su Proc. IEEE DATE 2002 – Design, Automation and Test in Europe,
Paris, France, March 4-8, 2002.

Capitoli di libro con comitato di revisione internazionale

[C1]                M.Bombana, F.Ferrandi,
“Design Methodology for Complex VLSI Devices”,
Practical Formal Methods for Hardware Design”,
C.D. Kloos, W. Damm (Eds), Berlin: Springer-Verlag 1997, ISBN 3-540-62007-9, pp. 7-22.
(versione estesa e rivista di [B15] e [B17])

[C2]                M.Bombana, P.Cavalloro, F.Ferrandi, F.Salice,
“Italtel application of the FORMAT Design Flow”,
Practical Formal Methods for Hardware Design”,
C.D. Kloos, W. Damm (Eds), Berlin: Springer-Verlag 1997, ISBN 3-540-62007-9, pp. 132-158.
(versione estesa e rivista di [B15] e [B17])

[C3]                D.Corvino, I.Epicoco, F.Ferrandi, F.Fummi, D.Sciuto,
“Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement”,
Electronic Chips & Systems Design Languages”,
Jean P. Mermet (Eds), Kluwer Academic Publishers, Boston, ISBN 0-7923-7311-1, March 2001.
(versione estesa e rivista di [B26] e [B28])

PhD thesis

[D1]                F.Ferrandi,
“Metodologie di Supporto alla Progettazione di Sistemi Digitali Testabili”,
Ph.D. thesis, DEI, Politecnico di Milano, February. 1997.

Altre pubblicazioni

Rapporti interni

[F1]                F.Ferrandi,
“Generazione automatica di alberi di clock per circuiti elettronici”,
Internal Report n. 94-071, 1994.

[F2]                C.Bolchini, F.Ferrandi, F.Salice, D.Sciuto,
“An Extension to Boolean Equations and Inequalities Based on Binary Decision Diagrams”,
Internal Report n. 96-018, 1996.

[F3]                G.Buonanno, F.Ferrandi, D.Sciuto,
“BDD Based Algorithms for Testability Analysis of Data-Path Architectures”,
Internal Report n. 96-020, 1996.

[F4]                G.Buonanno, F.Ferrandi, L.Ferrandi, D.Sciuto,
“Test Cost Estimation from Behavioral VHDL Descriptions”,
Internal Report n. 96-039, 1996.

[F5]                F.Ferrandi,
“Formal Design Methodology and Application to Complex VLSI Devices”,
Internal Report n. 96-134, 1996.

[F7]                G.Buonanno, F.Ferrandi, D.Sciuto,
“Testability Analysis of Pipelined Data Paths”,
Internal report.

[F8]                F.Ferrandi, F.Fummi, L.Pozzi,
“Configuration Specific Test Generation for FPGA Logic”,
rapporto interno 0701-99, DSET, Università di Verona.

[F9]                F.Ferrandi F.Fummi D.Sciuto,
“Design Verification of VHDL Specifications through Functional Testing”,
rapporto interno 0802-99, DSET, Università di Verona.

[F10]                F.Ferrandi, F.Fummi, D.Sciuto,
“Symbolic Sequential Test Sequences Compaction”,      
Internal Report.

[F11]                “Formality and FormalPro Evaluation Report”, S. Catenacci G. Ferrara, E. Trucco, F. Ferrandi, Siemens ICN internal report, September 2000.

 

Rapporti Tecnici Progetti ESPRIT

[G1]                M.Bombana, P.Cavalloro, C.Costi, G.Zaza, C.Bolchini, G.Buonanno, F.Ferrandi, D.Sciuto,
“Testability Analyzer”,
Technical Report of WP2.3-4, Esprit project n. 5020 - PATRICIA, December 1992.

[G2]        G.Bezzi, A.Balboni, M.Bombana, P.Cavalloro, C.Costi, G.Zaza, C.Bolchini, G.Buonanno, F.Ferrandi, D.Sciuto,
“Application of the PATRICIA tools: the user's point of view”,
Technical Report of WP2.4-1, Esprit project n. 5020 - PATRICIA, March 1994.

[G3]                M.Bombana, P.Cavalloro, C.Costi, G.Zaza, C.Bolchini, G.Buonanno, F.Ferrandi, D.Sciuto,
“Assessment of testability properties from VHDL descriptions”,
Technical Report of WP2.3-5, Esprit project n. 5020 - PATRICIA, March 1994.

[G4]                C.Bolchini, G.Buonanno, F.Ferrandi, F.Fummi, D.Sciuto, M.Bombana, P.Cavalloro, P.M.Borrego,
“Definition of methodology for testability analysis at the RTL and CDFG levels. Requirement specs for Functional Pattern Quality Evaluator.”,
Technical Report of Deliverable 2.3.A, Esprit project n. 20616 - REQUEST, April 1996.

[G5]                F.Ferrandi, F.Fummi, D.Sciuto,
“Report on testability analysis at the CDFG and RT levels – COMMIT –”,
Technical Report of Deliverable 2.3.C – I, Esprit project n. 20616 - REQUEST, May 1997.

[G6]                F.Ferrandi, F.Fummi, D.Sciuto,
“Report on test pattern generation and testable design for IFSMs– IFSMTest –”,
Technical Report of Deliverable 2.3.C – III, Esprit project n. 20616 - REQUEST, May 1997.