Prof. William Fornaciari




Short CV

text William Fornaciari is Associate Professor at Politecnico di Milano, Dipartimento di Elettronica e Informazione. He published six books and over 150 papers in international journals and conference proceedings, collecting five best paper awards, one certification of appreciation from IEEE and holds two international patents on low power design solutions. Since 1993 he is member of program and scientific committees and chair of international conferences in the field of computer architectures, EDA and system-level design. Since 1997 has been involved in 13 EU-funded international projects and he has been part of the pool of experts of the Call For Tender No.964-2005 – WING – Watching IST INnovation and knowledge, studying the impact of FP5 and FP6 expenditure for the EC, in the perspective to support the identification of FP7 and Horizon2020 research directions.
Recently, he participated to the MULTICUBE project for design space exploration and to the IP WASP on wireless sensor networks. In FP7 he has been workpackage leader for the IP COMPLEX project and Project Technical Manager of 2PARMA and also contributes to the Artemis SMECY project. Currently, still in FP7, he is project coordinator of the project HARPA on run-time management to achieve dependable performance and Workpackage leader of the CONTREX project on design of systems with mixed criticalities. He is also project reviewer for the European Commission and national research bodies in Europe. During the last 20 years he has worked as consultant for both management and technical issues for many ICT industries, gaining a relevant experience in technology transfer and product development. His current research interests include embedded systems design methodologies, real-time operating systems, energy-aware design of sw and hw, runtime management of resources, reconfigurable computing and wireless sensor networks, design and optimization of multi-core systems, NoC design and optimization, reliability.

Scientific Interests

La mente è come un paracadute. Funziona solo se si apre [Albert Einstein]

Thermal Modeling of Multi-core SoCs

Multi-core architectures are a promising paradigm to cope with increasing performance requirements under reliability and temperature constraints. Thermal optimization can be classified in design-time and run-time approaches. Static approaches focus on appropriate thermal-aware design of processor architecture and microarchitecture, while Dynamic Thermal Management (DTM) approaches rely upon run-time techniques such as DVFS or task migration.
Our research group focuses on analysis and exploitation of thermal coupling information for proper thermal status estimation, as a smart support for DTM policies. Target architectures are multi-core and many-core with Network-on-Chip support.
A toolchain, named HANDS, collecting and extending existing tools, has been developed to support such type of analysis.

Energy Aware Design of Software

The energy budget for most embedded systems is more and more becoming dependent on the software components of the application. For this reason, an early and as accurate as possible estimate of the power consumed by the execution of software is crucial, both for optimization and feasibility purposes. Such an estimation is especially useful if performed at source code level, that is the level of abstraction at which the application is conceived by the developer. Our group has been active in the field of software energy estimation and optimization for 15 years, during which we developed several methdologies and toolchains to support analysis and optimization. The analysis is focused on all the components of a software application: algorithms, drivers and hardware interfaces, operating systems and third party binary libraries. For each of such components we have developed specific methodlogies that can be easily retargeted for different microprocessor architectures, operating systems and compilation toolchains. The key idea behind most of our approaches lays in the decoupling of the analysis into a static characterization and modelling pahse and a dynamic analysis phase. Given elementary execution time and power consumption figures for a specific architecture, our models and tools can provide rapid yet accurate and data dependent estimates for an application without the need to resort to ISS or other forms of low-level simulations. From the experience acquired studying the estimation problem we founded our techniques for energy and performance optimization. It is known that compilers are continuously refining and improving optimization passes to produce better and more efficient code. Nevertheless, all transformations performed by the compiler need to maintain the semantics unchanged and to this purpose extremely complex and time consuming analyses are necessary. Furthermore, even though research activities are trying to remove this limitation, most of the optimizations are limited to basic blocks, and functions. Only limited program-wide optimization opportunities can be exploited. The methodology that we propose faces the problem from a different point of view, tryng to combine fast and approximate automated analyses with the deep and abstract knowledge the programmer has of his application. Our optimization methodology and the supporting engine does not perform any transformation on the code - which would require a full compiler infrastructure - but rather explores potential optimization opportunities at a higher level of abstraction, leaving the decision whether to transform the code or not to the programmer. While on one hand this require manual code modification, on the other hand such an approach allows analyzing the code in more complete - yet approximate - manner and integrating the results of such analyses with structured design exploration techniques and a suitable, ad-hoc, rule-based inferential engine. Most of the techniques and models are supported by SWAT - SoftWare Analysis Toolchain, an set of tools based on the LLVM Compiler Infrastructure.

Reliability and NBTI

Reliability is becoming the major design goal of any high-performance microelectronic system. As technology scales down and operating temperatures increase, the reliability of the systems gets affected. Reliability (MTTF) has an exponential dependance on temperature, and Negative Bias Temperature Instability (NBTI) is becoming the major concern in scaled technologies. While reliability can generally benefit from higher-level thermal optimizations, great opportunity is given at microarchitecture-level for NBTI mitigation. Purpose of our research is to provide architecture and microarchitecture techniques aiming at minimizing the stress of PMOS devices for NBTI mitigation.
Our research focuses on superscalar processor architectures and Network-on-Chip routers microarchitecture.
This investigation is carried out as part of the HANDS research project.

Run-Time Resource Management in Multi-core Architectures

Resource management meand looking for the optimal tradeoff between Quality of Service and resource availability. Modern systems have shared hardware resources (e.g., many cores) and fairly mixed applications (workloads) competing for them. The scenario is not easy to be optimized since it is rather unpredictable in the behavior (use cases) and there is a strong competition for the resources and several objectives to fulfill, such as power and thermal problems, run-time issues, data and user dependent behavior of the applications, process variation, etc. Simple (SW) solutions are required to support frequent change of use-case, also suitable for critical and best-effort applications, capable to operate on a system-wide perspective, not only focusing on a single application needs. This is one step ahead with respect to the simple operating system, which will be enhanced with such additional capability to adapt and tune at run-time.

BBQ is our framework, cooperating with existing operating systems, capable to modify the platform setting and to allocate the resources (e.g. memory, CPUs, communication resources) to the applications, according to flexible and customizable figures of merit (e.g. the nature of the application, performance, energy and power, etc).

Operating Systems

Analysis and design of operating systems has been tackled in many ways during the last decade of research. Currently the main focus is on the:

  • Energy characterization of OSs
  • Operating systems for embedded applications, including those for WSNs (a prototype is developed to run on top of PoliNode)
  • Power/Thermal/Energy management for single and multi-cores (one patent pending)
  • Task scheduling for soft real time


As VLSI technology scale becomes smaller and the number of modules on a chip increases, on-chip communication solutions are evolving in order to support the new inter-module communication demands. Moreover, traditional solutions, such as bus-based, cross-switched or point-to-point communications and their combinations have shown their scalability limit, and are no longer adequate for sub-micron technologies. In this scenario, where inter-module communication is gaining even more importance, Network-on-Chip is emerging as a promising technology and seems to provide good scalability, reliability and performance properties. However, the design of NoCs faces micro-architectural engineers with several important trade-offs, such as topology selection, routing strategy selection, application mapping, thermal, low power and reliability issues. Moreover, even if a lot of work has been done in this field, the hugeness of this research area presents a number of aspects that still have to be investigated. This research focuses on power/performance, reliability and thermal aspects in emerging Network-on-Chip interconnection system for multi-core architectures. In particular the effort is devoted to heterogeneous NoC design and optimization considering both hardware/synthesis aspects as well as formal model methodologies using queuing theory.
This investigation is carried out as part of the HANDS research project.

Wireless Sensor Networks

Wireless Sensor Networks (WSNs) suffer from serious trade-offs between the need for energy-efficiency and functional goals like easiness, completeness, reliability and correctness in the application design and management. Notwithstanding the long research history on the field, this technology finds it hard to leave behind the merely academic perimeter and actually creep in industrial and civil acceptance, although it is still considered as one of the most promising solution for all those scenarios in which pervasive computing could be used for monitoring and control purposes. The main reason for this “low acceptance” in real applications lays on the steep knowledge curve that a programmer or an engineer should climb in order to acquire the tools for dealing with this networks, whose management requires a deep spectrum of competences, both vertically, from the low-level hardware and radio details to distributed application design, and horizontally, from communication and electronics to sensing and computer science. Moreover, all these aspects are strictly related among each other and the market of the WSNs is very fragmented, with a myriad of nodes, operating systems and protocols each presenting specific issues, also specific programming languages and interfaces, often very far from general-purpose programming environments, the greatest part of programmers and engineers are familiar with. The challenge is to seek for abstraction layers which can manage the trade-off between non-functional aspects, like energy consumption optimization, and functional goals as programmability, reliability and easiness of management, striving to get the programmers rid of at least a part of the knowledge complexity required for addressing WSNs’ issues.
The main veins of research are so related to the multi-objective optimization of functional and non-functional goals for task allocation in Wireless Sensor Networks on one hand, and the improvement of hardware and operating system layers in a direction that could provide a background management of the energy efficiency and other non-functional aspects, while providing to the programmers an interface as near as possible to general-purpose and user-friendly application environments.
In this direction places the project PoliNode on Miosix, an Hardware and OS architecture completely made in Polimi, whose main objectives are the realization of a node architecture capable of balancing high-performances and ultra low-power, given the desired computing and memory requirements, joined to higher level programming thanks to the availability of C and C++ standard programming and standard libraries on-nodes.

Recent Talks

  • W.Fornaciari, Management of mixed criticality and reliability at run-time: the HARPA approach, Thematic Session on mixed criticality/reliability, HiPEAC CSW 2014, Barcelona, May 15, 2014.
  • W.Fornaciari, Run-time management of multi-core architectures using the BBQ framework: Targeting Applications and Platform “Variability” Challenges, ChipEx14, The Annual Conference of the Israeli Microelectronics Industry, Tel Aviv, April 30, 2014.
  • W.Fornaciari, Overview of competencies on Embedded System and Computer Architecture Fostering Innovation for Cyber-Physical Systems, Advanced Computing & Manufacturing: Opportunities under Horizon 2020 LEIT-ICT Work Programme 2014/15 and the regional dimension, February 19-20, Brussels, 2014. Link on CORDIS. Competencies for Projects @ POLIMI
  • W.Fornaciari, Day 1 - Success stories of technology adoption - 2PARMA, Day 2- Session 2: Embedded Multi-Core Platforms - taking stock of achievements and economic perspectives: 2PARMA and HARPA , Cyber-Physical Systems: Uplifting Europe's innovation capacity, Brussels, 29 – 30 October 2013 Conference wesite, Flyer, day2 2PARMA, day2 HARPA, day1 2PARMA.
  • W.Fornaciari, Targeting Applications and Platform “Variability” Challenges: The BarbequeRTRM approach, Keynote at ReCoSoC 2013, Darmstadt, Germany, July 11th, 2013. Recosoc Keynote Presentation
  • W.Fornaciari, 2PARMA Project, REFLECT and 2PARMA Fall 2012 School: Programming Paradigms for Multi–‐Core Embedded Systems, Freustadt, Germany, October 2-5, 2012. Presentation (pdf)
  • W.Fornaciari, P.Bellasi, G.Massari, System-Wide run-time resource management for multi-many cores in the 2Parma Project, Session on Power-Efficiency and Program Correctness Analysis for Scalable Multicores, HiPEAC Computing Systems Week April 2012, Göteborg, Sweden, April 24-25, 2012. Presentation (pdf). BBQ v.08 Video
  • W.Fornaciari, C.Brandolese, SWAT: A methodology and a tool for source level timing/energy estimation of software, Session on Mobile Systems, HiPEAC Computing Systems Week April 2012, Göteborg, Sweden, April 24-25, 2012. pdf
  • W. Fornaciari, Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach, Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), held in conjunction with the 7th. HiPEAC Conference, January 25, 2012, Paris, France. Presentation. BBQ Video (local). BBQ Video (youtube)
  • W. Fornaciari, P. Bellasi, BBQ: the 2PARMA Framework for Run Time Resource Management for Multi-Core Computing Platforms, Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms, held in conjunction with the 7th. HiPEAC Conference, January 24, 2012, Paris, France . Extended Presentation. Short presentation. BBQ Video (local). BBQ Video (youtube)
  • W.Fornaciari Design Space Exploration for Run-time Resource Management: the MULTICUBE view, Friday Workshop at DATE 2010 on “Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications”, March 12, 2010, Dresden, Germany.
  • W.Fornaciari, 2PARMA Overview, HiPEAC Innovation Event,Session on FP7 European Projects organized by Dr. Panagiotis Tsarchopoulos Project Officer of EC, May 3-5, 2010 Edinburgh, UK. Short_pres
  • W.Fornaciari, System-wide run-time resources management, Princeton University, USA, Organized by prof. Ruby Lee, December 15th, 2009. Presentation
  • W.Fornaciari, System-wide run-time resources management, NEC-Labs at Princeton, NJ, USA, Organized by M. Lajolo, December 16th, 2009.

Professional Activities (not purely academic...)

  • Technical Consultant for lawyers (CT - Consulente Tecnico) and Courts (CTU - Consulente Tecnico d'Ufficio)
  • Technology Scouting
  • Development of innovative systems (technology transfer)
  • Feasibility studies
  • Design of products with emphasis on effective exploitation of ICT technologies
  • Project management and team building
  • Impact analysis


For further infos and news, please, take a look at the INTERNATIONAL PROJECTS page

International (FP7)
  • HARPA - HARnessing Performance vAriability. How to cope with process variability and thermal problems to ensure reliable performance in multi-core systems. Kick-off September 2013
  • CONTREX - Design of embedded systems with mixed criticalities. Kick-off October 2013
  • 2PARMA - run time management at several abstraction levels of multi-core architectures and parallel applications. Completed in 2013. “ranked as success story”
  • COMPLEX - design of embedded systems, emphasis on fast design space exploration and energy optimization. Completed in 2013
  • SMECY - design of multi-core systems. Completed in 2013
  • MULTICUBE - Multi-objective Design Space Exploration for multi-core systems

Internal Projects

For further infos and news, please, take a look at the RESEARCH page

  • SWAT - SoftWare Analysis Toolchain. Set of tools based on the LLVM Compiler Infrastructure to extract performance and energy information from source level application code.
  • BBQ - Framework for run-time resource management for multi-core architectures (seats on Linux and Android). It provides both mechanisms and some policies (new can be plugged easily)
  • POLINODE - Full wireless node including OS layer, tailored to optimize power consumption and verification of safety properties of the applications
  • HANDS - Simulation toolchain for power-performance-thermal-reliability analysis and optimization of multi-core architectures underpinned by NoC communication sub-systems.