Prof. William Fornaciari


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HANDS (Heterogeneous Architectures and Networks-on-Chip Design and Simulation)

Continuous technology scaling of recent decade lead to an exponential increase in processor performance, and power consumption going as faster as clock rate growth. The transition to multi-core architectures introduced an opportunity for performance to grow faster than power consumption, with Network-on-Chip as the appropriate design paradigm to manage increasing performance and reliability requirements. Complex architectures have a huge amount of design parameters, and simulation represents the most accurate method to extract valuable information on the architecture, in order to provide and analyze optimization strategies early at the design stage. HANDS stands for “Heterogeneous Architectures and Networks-on-chip Design and Simulation”, a tool for computer architecture research with emphasis on multi-core processors and Network-on-Chip architectures. The tool targets performance, power, thermal and reliability analysis in a jointly fashion, through an appropriate simulation flow based on state-of-the-art cycle-accurate simulator (GEM5), power models (McPAT and Orion2.0) and thermal model (HotSpot). HANDS is designed for flexibility, and it allows for accurate early-stage estimation of microarchitecture and architecture design choices, e.g. reliability-driven dynamic instruction scheduling, thermal management, impact of floorplan and NoC design on temperature profile, NBTI mitigation and many others. Among the others, the following are the capabilities of the framework:

  • design-space exploration of power/performance and thermal/reliability trade-off in high-performance processor architectures
  • thermal/reliability design solutions and optimizations
  • exploration of power and thermal aspects in Network-on-Chip design
  • reliability projection as a function of temperature profile (independent MTTF modeling)
  • on-line NBTI estimation based on state-of-the-art models
  • impact of within-die random and systematic process variation on aging and performance
  • NBTI mitigation of units in a superscalar processor and routers in a Network-on-Chip

Keywords: Aging, power, performance, thermal, multi-core, Network-on-Chip, design space exploration, multi-core and many-core, energy optimization, reliability and NBTI

Methodology at the glance

HANDS is composed of a bunch tools that are widely used in the computer architecture research community, as well as new tools to support the complexity of the analysis. HANDS flow is composed of four different steps, starting from cycle-accurate simulation and leading to thermal map generation and reliability projection. Cycle-accurate simulation (GEM5) provides access statistics to architecture blocks: accesses to instruction fetch unit, number of committed integer instructions, number of stall cycles in the pipeline and the like. Memory-related statistics are also acquired providing a system-wide perspective. Accurate power consumption estimates are employed by well-known processor and router power models (McPAT and Orion2.0). Last, temperature profile is computed using floorplan physical information and power statistics, in conjunct with state-of-the-art RC equivalent thermal model (HotSpot). Reliability projections are performed according to analytical models of MTTF for major failure mechanisms: electro-migration, stress-migration, thermal cycling and NBTI. Also, within-die process variation is accounted for. Temperature and reliability back-annotation can be used to provide flexible temperature and reliability oriented run-time management strategies.

Results and current activities

  • Availability of the HANDS toolchain to other research groups as open-source software
  • Cooperation to setup funded projects covering aspects related to thermal related reliability issues and management of the power consumption
  • Availability to cooperate with other research groups and industries to extend and/or integrate the blocks composing the HANDS toolchain

Main References & Documents

  • S. Corbetta, W. Fornaciari D. Zoni, Thermal-Performance Trade-off in Network-On-Chip Architectures, IEEE SoC 2012, The International Symposium on System-on-Chip, Tampere, Finland October 11-12, 2012. pdf_tmp. Keywords: Thermal management, Multi-core, SoC, Networks-on-Chip, system simulation, reliability, design flows.
  • W.Fornaciari, D.Zoni, A Sensor-less NBTI mitigation methodology for NoC architectures, SOCC'2012 25th IEEE International System-on-Chip Conference, Niagara Falls, New York, USA, September 12–14, 2012. pp ??. pdf_tmp
  • S. Corbetta, W. Fornaciari, D. Zoni, A Temperature and Reliability Oriented Simulation Framework for Multi-Core Architectures, IEEE Computer Society Annual Symposium on VLSI (ISVLSI2012), University of Massachusetts, Amherst, USA, August 19-21, 2012. pp 51-56. pdf. DOI: http://dx.doi.org/10.1109/ISVLSI.2012.22. ISSN: 2159-3469, ISBN: 978-1-4673-2234-8. Keywords: Thermal management, Multi-core, SoC, Networks-on-Chip, system simulation, reliability, design flows.
  • S. Corbetta, W. Fornaciari, D. Zoni, HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation, IEEE ISLPED'12 International Symposium on Low Power Electronics and Design, Redondo Beach, California, USA, July 30-August 1, 2012. pp???. pdf. Keywords: Thermal management, Multi-core, SoC, Networks-on-Chip, system simulation, reliability, design flows.
  • S. Corbetta, W. Fornaciari, NBTI Mitigation in Microprocessor Designs, in Proceedings of the 22nd edition of the Great Lakes Symposium on VLSI (GLSVLSI '12), Salt Lake City, Utah, USA, May 3-4 2012 pp 33-38. pdf. Keywords: reliability, process variation, NBTI, thermal modeling, design space exploration, energy aware design.
  • S. Corbetta, W. Fornaciari, NBTI Mitigation in Microprocessor Designs, in Proceedings of the 22nd edition of the Great Lakes Symposium on VLSI (GLSVLSI '12), Salt Lake City, Utah, USA, May 3-4 2012 pp 33-38. pdf. Keywords: reliability, process variation, NBTI, thermal modeling, design space exploration, energy aware design.
  • S. Corbetta, W. Fornaciari, Estimation of thermal status in multi-core systems, 2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011), May 15-18, Rio de Janeiro, Brazil, 2011, pp. 1660-1663. DOI:http://dx.doi.org/10.1109/ISCAS.2011.5937899. Keywords: Thermal management, Multi-core, SoC. pdf

HANDS Research Team


Politecnico di Milano
DEI - Dipartimento di Elettronica e Informazione
Via Ponzio 34/5
20133 Milano, Italy



Project Manager and Contact

Prof. William Fornaciari
fornacia@elet.polimi.it
http://home.dei.polimi.it/fornacia
phone: +39 02 2399 3504

Main Investigators and Chief developers