Prof. William Fornaciari


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PoliNode and research on WSNs

One of the most critical drawback of Wireless Sensor Networks, limiting their widespread diffusion outside the academic boudaries, lays on the lack of programming flexibility and in the hardness to trade-off applicative effectiveness and available energy and resources on nodes.
Even though many platforms and Operating Systems are available today for Wireless Sensor Networks, the high-end, more powerful nodes often suffer from heavy energy consumes and do not completely support standard programming, memory protection and efficient dynamic programming of nodes. On the other hand, small and ultra-low power nodes are characterized by strong constraints on the available resources and can be equipped with minimal monolithic or layered-based operating systems, the use of which often requires a programmer to deal with specific non-standard variants of programming languages and libraries. This small nodes, moreover, present a general lack of flexibility for dynamic programming nodes and do not support important security issues like memory protection. Very few or hardly any of the available OS for WSN, moreover, support full-blown processes and standard languages and libraries.
The main goal of the project PoliNode is to overcome such obstacles, in particular:

  • to provide both hardware and OS layers powerful and abstract enough to enable programming styles as near as possible to general-purpose paradigms, including standard C and C++ languages and libraries, hardly ever supported by actual sensor nodes platforms;
  • to enable more flexibility to the developers in designing their applications, through reasonable large memory and computing power;
  • to manage the duty cycle between active and idle periods of the Microcontroller and Peripherals, as well as tasks’ scheduling and radio communications and synchronization, in such a way that low power performances are enforced, against the more powerful and so consuming hardware underneath.

The PoliNode Architecture and Hardware


The objective of the project PoliNode is to investigate the possibility of merging the advantages of high-end platforms and Operating Systems, while enforcing low-power management at OS and software layers and integrating, at the same time, some lacking features like processes support, with multitasking and hibernation, standard languages and libraries, memory protection and efficient dynamic reprogramming mechanism. The whole architecture is designed to minimize the memory usage and to guarantee lightweight kernel support in sleeping, idling or stand-by cycles of the microcontroller.
At hardware level, at a general glance, the architecture encompasses:

  • An high-end microcontroller with memory protection and enough available RAM and FLASH;
  • An external MRAM to support complete processes’ hibernation, enabling optimal duty-cycling of the microcontroller and in particular complete stand-by periods, without losing the status of the applications;
  • An ultra-low power transceiver (the synchronization and control phases of the radio is enforced through a lightweight service of the OS that does not entail the cost of the microcontroller in full-active state);
  • Interfaces towards peripherals, the access to which is eventually mediated by smart-drivers implemented at OS level.

The presence of such features assures high performances as well as the possibility to provide general-purpose like programming interfaces to the users, but surely presents higher energy costs if compared to ultra-low power platforms. To optimize the power consumption in order to achieve low-cost performances, the OS layer will be in charge of enforcing low-power resource management policies. The presence of the external MRAM, in particular, serves to this goal enabling loss-free status saving when bringing in stand-by the microcontroller to optimize its duty-cycle (especially possible in ambient monitoring and other non real-time scenarios). This approach offers promising performances thanks to the low-power cost profile of MRAM in retained mode.

The PoliNode Software Layer

The OS layer of the PoliNode will be based on Miosix OS. This OS presents a very small footprint , as well as multithreading and standard C and C++ programming support. Moreover, this operating system provides a very efficient and innovative scheduling mechanism based on Control Theory, a class of models and theories belonging to Automation Control but which reveals itself unexpectedly well-fitting also for OS scheduling. Miosix OS will be integrated with processes’ support and lightweight dynamic linking features (based on standard, optimized ELF), with memory protection and optimized shared libraries for standard C and C++ programming. This shared libraries will be an hybrid between static and dynamic libraries, eventually shared between the OS and the applications (to minimize the memory requirements) and possibly avoiding the need for a symbol table. Moreover, the applications using the shared libraries should avoid to reserve space in memory for all the data of the used libraries, managing to store space just for the needed data. At OS level will be implemented also the power-management and duty-cycling logic, the smart drivers for the peripherals and the power-efficient radio and sensors’ data management. The OS will be also capable of operating in two task mode: one offering full support and the other enforcing a lightweight configuration for managing the synchronization and control operations in idle and low-power periods of the microcontroller. On top of the operating system, a distributed scheduling logic, possibly based on Control Theory, will be implemented supporting distributed optimal task allocation for functional and non-functional (power) optimization.

PoliNode Development Team


Politecnico di Milano
DEI - Dipartimento di Elettronica e Informazione
Via Ponzio 34/5
20133 Milano, Italy


Project Manager and Contact

Prof. William Fornaciari
fornacia@elet.polimi.it
http://home.dei.polimi.it/fornacia
phone: +39 02 2399 3504

Chief Investigator
Responsibles for Design and System Integration

Software Allocation and Relocation in WSNs

The present work concentrates on theformulation of a model and anheuristic for generating, respectively, optimal and sub-optimal software allocations to maximize the lifetime of Wireless Sensor Networks. This is achieved by minimizing and balancing the energy consumption, while preserving the completeness of the application and the resilience against nodes’ faults. In the considered scenario a node can schedule and execute multiple functions, either stored on its Flash memory ordynamically retrieved from the base station or the cluster head, througha dynamic reprogramming mechanism. Execution is guaranteed by a distributed scheduling mechanism, capable of orchestrating the execution of a given function among all the nodes on which that function is run, so that its execution frequency is guaranteed and the overall energy consumption minimized by exploiting parallelism among nodes. Both the model and the heuristic include constraints on the available memory and thedesiredexecution frequency offunctions, as well as routing and overhearing issues. The main result of the proposed work is a framework to efficiently define the software allocation on a WSN under power-consumption constraints, encompassing also more evolved architectures, equipped with a dynamic reprogramming mechanism, multitasking nodes and a distributed scheduler.

Main References & Documents

  • C.Brandolese, W.Fornaciari, L.Rucco, F.Terraneo, Enabling Ultra-Low Power Operation in High-End Wireless Sensor Networks Nodes, CODES+ISSS 2012 International Conference on Hardware/Software Codesig and System Synthesis, Tampere, Finland, October 7-12, 2012. pdf_tmp
  • C. Brandolese, W. Fornaciari, L. Rucco, D. Zoni, Towards Energy-Efficient Functional Configuration in WSNs, International Conference on Programmable Devices and Embedded Systems (PDES'12), Brno, Czech Republic, May 23th - 25th, 2012, pp.?? pdf_tmp.
  • C. Brandolese, W. Fornaciari, L. Rucco, D. Zoni, Power-Efficient Software Allocation in Wireless Sensor Networks Design, Automation & Test in Europe (DATE’12), Poster paper at the Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany, March 12-16, 2012. pdfA4, pdfA1. Keywords: Wireless Sensor Networks, software power optimization, task allocation, formal models, systems level optimization, run-time adaptation, energy efficient design.