Prof. William Fornaciari


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SWAT (Software Analysis Toolset)


Demo of SWAT at Design, Automation & Test in Europe (DATE’12), Dresden, Germany, March 12-16, 2012. Booth EP8, Thursday, March 15, 10:00 - 12:30. SWAT Flyer DATE'12


  • W.Fornaciari, C.Brandolese, SWAT: A methodology and a tool for source level timing/energy estimation of software, Session on Mobile Systems, HiPEAC Computing Systems Week April 2012, Göteborg, Sweden, April 24-25, 2012. pdf
  • S. Bocchio, C. Brandolese, S. Corbetta, W. Fornaciari, A Methodology and a Case Study of Dynamic Power Management for Embedded Systems, FETCH2012 - 6th Winter School on Design Technologies for Heterogeneous Embedded Systems (www.fetch-conference.org), January 9-12, 2012, Alpe d’Huez, France. Keywords: Low power systems, embedded systems, wireless sensor networks, design methodology, software energy optimization, power islands, dynamic power management. Presentation pdf.

SWAT Development Team


Politecnico di Milano
DEI - Dipartimento di Elettronica e Informazione
Via Ponzio 34/5
20133 Milano, Italy


Project Manager and Contact

Prof. William Fornaciari
fornacia@elet.polimi.it
http://home.dei.polimi.it/fornacia
phone: +39 02 2399 3504

Chief Developer

Prof. Carlo Brandolese

SWAT has been developed within the COMPLEX project

SWAT analysis and estimation toolchain


The SWAT analysis and estimation toolchain provides support for early inspection of the non-functional properties of an application starting from its C source code. The key idea behind the flow is decoupling the underlying models into:

  • A static model of the source code structure that only accounts for the semantics of the applicaction
  • A target characterization library specifying the elementary timing and power figures of the target processor
  • A data dependent model of the application behaviour constituted by an LLVM basic-block profiling


The back-end of the flow, constituted by a post-processor, two analyzers and a back-annotator, combines such models to derive a complete static and dynamic characterization of the application. The toolchain produces a detailed, fine-grained easy-to-navigate report collecting all the main analysis results.













SWAT optimization toolchain

Fuzzy optimization



Based on the same front-end of the estimation flow and using the results extracted from the dynamic models and the execution traces, the main optimization flow apply a set of fuzzy rules on selected portions of the application to suggest the most promising transformations to apply.










Compiler Optimizations



A second optimization flow explores compiler optimization options in order to determine the transformation mix that best fits the specific applicatio. To this purpose, the MOST design space exploration engine is used to generate sets of transformation mixes for the LLVM optimizer until the best optimization recipe is found.






SWAT Toolchanin achievements and results

SWAT provides a set of models and a fully automated methodology for characterization, analysis and execution time, energy consumption estimation and optimization. The characterization flow allows automatically building the target microprocessor models needed to support the estimation flow. The process is based on static code analysis and requires limited data on the target processor. The analysis flow is based on a static representation of the source code in LLVM pseudo-assembly language, and on profiling data derived from code executions, either on a generic host machine or on the target platform. The analyses performed range from source code structure (functions, static call graph, basic blocks, CDFG, …) to IR statistics (instructions, classes of instructions, load/store counts, …) to more informative and complex analyses such as inlining candidated, type promotion/demotion, memory pressure, stack size, basic-block and function level energy and execution time distributions. The SWAT flow allows to back-annotate energy and timing figures onto the source code with a very high accuracy.
Different tools are provided by the optimization flow:

  • Optimal transformation recipe derived through DSE
  • High-level parametric DSE
  • Abstract and application-wide optimization hints


Currently the flows and models have been validated for the STMicroelectronic ultra low power ReISC III core using instruction-set simulation results as reference. Accuracy of the results is promising and the run-time of the estimation toolchain is more 400 times faster than ISS.






Main References

Modeling of software power consumption:

Background on the impact of source level code transformations: