I am an assistant professor at Politecnico di Milano, Italy.
I have a Ph.D. in Information Technology from Politecnico di Milano (2011). I was research assistant at Politecnico di Milano (2011-2013), and postdoctoral research scientist at Columbia University (2013-2016) and at the Università della Svizzera italiana (USI) (2016-2018). I have been visiting researcher at NanGate (2009-2010), Chalmers University of Technology (2012), Delft University of Technology (2016-2017), and more recently New York University (2017-2018).
My research interests include high-level synthesis, reconfigurable systems, and system-on-chip architectures, with emphasis on memory and security aspects.
I actively participate (or participated) to several projects sponsored by European Union (hArtes, Synaptic, FASTER, CERBERO) and a multi-university research center (C-FAR) supported by Semiconductor Research Corporation and DARPA.
I delivered invited keynotes (FPL 2017), tutorials (FPL 2017, CASES 2017, FPT 2017) and several talks on high-level synthesis, system-on-chip design, and hardware security. I served as program chair of IEEE EUC 2014. I serve on the several program committees of several conferences in the area of embedded systems, CAD, and reconfigurable architectures (DAC, DATE, CASES, ICCD, FPL).