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Associate Professor
Politecnico di Milano
Dipartimento di Elettronica, Informazione e Bioingegneria Leonardo Da Vinci 32, I-20133, Milano (Italy)
Tel.: +39-02-2399-3692
Fax: +39-02-2399-3411 
ANTAREX - Project Coordinator (Sep. 2015 - Aug. 2018)

Cristina Silvano is Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria. She received the Laurea Degree (M. Sc.) in Electrical Engineering from Politecnico di Milano in 1987 and the Ph. D. Degree in Computer Engineering from University of Brescia in March 1999.

At the early stages of her career, she was part of the Bull-IBM Research team for the design of a family of scalable multiprocessor systems based on the PowerPC architecture, introduced in 1992 by Apple-IBM-Motorola. In 1996, she started investigating power optimization and estimation techniques for embedded architectures applied to the Lx/ST200 VLIW processors, designed in partnership between HP Labs and STMicroelectronics and widely used in a variety of embedded media processing products. Since then, she started a continuous research collaboration with STMicroelectronics and she was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008).

Her current research interests are in the design of energy-efficient computer architectures with special emphasis on design space exploration and application autotuning for embedded manycore architectures. In these areas, she has coordinated two EU-funded projects (MULTICUBE and 2PARMA). She is also active in the area of autotuning and adaptivity for energy-efficient High Performance Computing systems. On this topic, she is currently the Scientific Coordinator of the H2020 FET-HPC ANTAREX research project. She has recently been nominated Project Manager of the IBM/Politecnico di Milano Collaborative Innovation Center on Big Data Analytics (2015-present).

She is an active contributor to the scientific community and she regularly serves as Member (or Track Chair) of the Program Committee of several top-level conferences such as ICCAD, DAC, DATE, NOCS, HPCA, MICRO, ASAP, FPL. Recently she was Program Chair of FPL 2015, the 25th International Conference on Field Programmable Logic and Applications. She was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. She was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). She is Associate Editor of the ACM Transactions on Architecture and Code Optimization. She served as independent expert reviewer for the European Commission and for several science foundations.

She has published more than 160 publications in peer-reviewed international journals and conferences, four books and has made several industrial patent applications. She has been named an IEEE Fellow (since 2017) from the IEEE Board of Director “for contributions to energy-efficient computer architectures”. She is member of ACM and member of HiPEAC Network of Excellence.           

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Last Update 01/02/17