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ACA COMO COURSE SCHEDULE AA 2016-2017
(PRELIMINARY VERSION --- TO BE UPDATED)

LESSON   DATE TOPIC AND SLIDES
Intro Tuesday 7 MARCH 2017 

INTRO

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Lesson 1 Tuesday 7 MARCH 2017 


Lesson 1: Pipelining: Basic Concepts
      Architectecture of the MIPS Pipeline processor

EXE Thurs. 9 MARCH 2017 

EXERCISES oN Pipelining Optimization:

FIRST EXERCISE ON PIPELINING

FIRST ASSIGNMENT on PIPELINING -EX1A

Lesson 2 Tuesday 14 MARCH 2017  Lesson 2: Branch Prediction Techniques
      The problem of control hazards
      Static & Dynamic branch prediction techniques
EXE Thursday 16 MARCH 2017 

MORE EXERCISES oN Pipelining Optimization
(INCLUDING THE SOLUTION OF FIRST ASSIGNMENT and SECOND EXE)

Lesson 3 Tuesday 21 MARCH 2017  Lesson 3: Instruction Level Parallelism - Part I
     Introduction to ILP
     Dependences and Hazards
     Dynamic Scheduling vs Static Scheduling
    Superscalar vs VLIW Processors
EXE Thursday 23 MARCH 2017 

EXE ON PIPELINING OPTIMIZATION CONT'D
(THIRD EXE)

  Tuesday 28 MARCH 2017  LeSSON SUSPENDED
EXE Thursday 30 MARCH 2017  EXERCISE on OUT-OF-ORDER MULTISTAGE PIPELINE  NEW VERSION

EXERCISE ON MULTIPLE ISSUE
 

Lesson 4 Tuesday 4 APRIL 2017  Lesson 4: Instruction LEVEL PARALLELISM - PART II
     DYNAMIC SCHEDULING: SCOREBOARD Algorithm
 
Lesson 5 Tuesday 4 APRIL 2017 

Lesson 5: Instruction LEVEL PARALLELISM - PART III
     DYNAMIC SCHEDULING: TOMASULO Algorithm

EXE Thursday 6 APRIL 2017  Dynamic Scheduling Techniques: ScoreboARD vs. Tomasulo RECAPExamples of application of dynamic scheduling techniques: SCOREBOARD
Lesson 6 Tuesday 11 APRIL 2017  LESSON 6:
      Instruction Level Parallelism - Part IV
      Register Renaming
      EASTER VACATION PERIOD
EXE Thursday 20 APRIL 2017  Dynamic Scheduling Techniques: ScoreboARD vs. Tomasulo RECAP

Examples of application of dynamic scheduling techniques: TOMASULO

  Thursday 20 APRIL 2017  ASSIGNMENT OF PROJECTS and PRESENTATIONS TO STUDENTS
      INTERMEDIATE SUSPENSION PERIOD
Lesson 7 Tuesday 9 MAY 2017 

LESSON 7: Instruction Level Parallelism - Part V
      Reorder Buffer and Speculation
 

Lesson 8


Lesson 9
Thursday 11 MAY 2017  LESSON 8:
Instruction Level Parallelism - Part VI
Static Multiple-issue Processors:
VLIW (Very Long Instruction Word) Architectures

LESSON 9:
Instruction Level Parallelism - Part VII
VLIW Code Scheduling
 

Lesson 10 Thursday 18 MAY 2017  Lesson 10: Introduction to Performance Evaluation
EXE Thursday 18 MAY 2017  EXERCISES on Performance Evaluation
EXERCISES on PERFORMANCE of MEMORY HIERARCHY
Lesson 11 Tuesday 16 MAY 2017  Lesson 11A: Introduction to cache memories: Basic Concepts (PART I)

Lesson 11B: Memory Hierarchy: Advanced Concepts (PART II)

Lesson 11C: Virtual Memory

SOME EXAMPLES ON CACHE MEMORIES

Lesson 12 Thursday 25 MAY 2017 
Lesson 12:
BEYOND ILP: MULTITHREADING

 
Lesson 13A Tuesday 30 MAY 2017  Lesson 13A: Introduction to Multiprocessors (PART I) new!
Lesson 12B Thursday 1 June 2017  Lesson 13B: Introduction to Multiprocessors (PART II)NEW!
Lesson 14A Thursday 15 JUNE 2017  LESSON 14A:
SIMD & VECTOR ARCHITECTURES NEW!
Lesson 14B Thursday 15 JUNE 2017 

LESSON 14B:
INTRO TO GP-GPUs

  Tuesday 20 JUNE 2017  Students Presentations
   

 
Rules for PROJECTS/PRESENTATIONS TO STUDENTS

PROJECTS/PRESENTATIONS TO BE COMPLETED BY JUNE 2017 - HARD DEADLINE (The project is OPTIONAL) -- MAX TWO PERSONS FOR EACH PROJECT

  • PROJECT RESULTS Presentation IN ENGLISH (SINGLE PERSON): Min 10 Max 12 slides in English (FORMAT: .PPT or .PDF) and 5 MIN DEMO

  • PROJECT RESULTS Presentation IN ENGLISH (TWO PERSONS): Min 15 Max 20 slides in English (FORMAT: .PPT or .PDF) AND 5 MIN DEMO

     

END OF COURSE