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International Conferences and Workshops with Peer Review

2016

  1. Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano: "Throughput balancing for energy efficient near-threshold manycores". The 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016: pp. 64-69, DOI

  2. Ioannis S. Stamelakos, Amin Khajeh, Ahmed M. Eltawil, Gianluca Palermo, Cristina Silvano, Fadi J. Kurdahi, "A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 484-489,  DOI PDF

  3. Cristina Silvano, Giovanni Agosta, Stefano Cherubin, Davide Gadioli, Gianluca Palermo, Andrea Bartolini, Luca Benini, Jan Martinovic, Martin Palkovic, Katerina Slaninová, João Bispo, João M. P. Cardoso, Rui Abreu, Pedro Pinto, Carlo Cavazzoni, Nico Sanna, Andrea R. Beccari, Radim Cmar, Erven Rohou: “The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems”. ACM Int. Conference on Computing Frontiers, CF’2016, Como, Italy, May 16-19, 2016: 288-293, DOI

  4. Cristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea Beccari, Luca Benini,  João Bispo, João M. P. Cardoso, Carlo Cavazzoni, Radim Cmar, Jan Martinovic, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna, and Katerina Slaninova, "AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems: The ANTAREX Approach", Proceedings of DATE 2016 IEEE/ACM Design and Test in Europe Conference, Dresden (Germany), March 14-18, 2016 URL  PDF  SLIDES

2015

  1. Davide Gadioli, Gianluca Palermo, Cristina Silvano, "Application Autotuning to Support Runtime Adaptivity in MulticoreArchitectures", Proceeding of XV International Conference on Systems, Architectures, Modeling, and Simulation, IC-SAMOS 2015. Agios Konstantinos, Samos, Greece, July 20-23, 2015, pp. 173-180 Link PDF Slides

  2. Edoardo Paone, Francesco Robino, Gianluca Palermo, Vittorio Zaccaria, Ingo Sander and Cristina Silvano, "Customization of OpenCL Applications for Efficient Task Mapping under Heterogeneous Platform Constraints", In Proceedings of DATE 2015 - International Conference on Design, Automation and Test in Europe. Grenoble, France. 9-13 March 2015. pp. 736-741. URL  PDF

2014

  1. Amir Hossein Ashouri, Giovanni Mariani, Gianluca Palermo and Cristina Silvano, "A Bayesian Network Approach for Compiler Auto-tuning for Embedded Processors", ESTIMedia 2014, The 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, New Delhi, India, October 16-17, 2014. DOI PDF Slides

  2. Davide Gadioli, Simone Libutti, Giuseppe Massari, Edoardo Paone, Michele Scandale, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, Giovanni Agosta, William Fornaciari, and Cristina Silvano. “OpenCL Application Auto-Tuning and Run-Time Resource Management for Multi-Core Platforms” Proceeding of 12th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2014. Milan, Italy, August 26-28, 2014, pp. 127-133. DOI PDF Slides

  3. Giuseppe Massari, Edoardo Paone, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, William Fornaciari, and Cristina Silvano. “Combining Application Adaptivity and System-wide Resource Management on Multi-Core Platforms”, Proceeding of XIVth International Conference on Systems, Architectures, Modeling, and Simulation, IC-SAMOS 2014. Agios Konstantinos, Samos, Greec, July 14-17, 2014, pp. 26-33. DOI PDF

  4. Edoardo Paone, Davide Gadioli, Gianluca Palermo, Vittorio Zaccaria, and Cristina Silvano. “Evaluating Orthogonality between Application Auto-Tuning and Run-Time Resource Management for Adaptive OpenCL Applications”, Proceeding of IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014, Zurich, Switzerland, June 18-20, 2014, pp. 161-168. DOI PDF Slides

  5. Giuseppe Massari, Edoardo Paone, Michele Scandale, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, Giovanni Agosta, William Fornaciari, Cristina Silvano: "Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures". Proceedings of Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Lecture Notes in Computer Science Vo. 8405, 2014, pp. 345-352. DOI PDF

  6. Cristina Silvano, Gianluca Palermo, Sotirios Xydis and Ioannis Stamelakos. “Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon” In Proceedings of DATE 2014 - Conference on Design, Automation and Test in Europe. Dresden, Germany. 24-28 March 2014. pp. 1-6. DOI PDF Slides

  7. Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. “DeSpErate: Speeding-up Design Space Exploration by using Predictive Simulation Scheduling”. In Proceedings of DATE 2014 - Conference on Design, Automation and Test in Europe. Dresden, Germany. 24-28 March 2014. pp. 1-4. DOI PDF

  8. Giovanni Mariani, Gianluca Palermo, Roel Meeuws, Vlad-Mihai Sima, Cristina Silvano and Koen Bertels. “DRuiD: Designing Reconfigurable Architectures with Decision-making Support”, In Proceedings of ASP-DAC 2014, 19th Asia and South Pacific Design Automation Conference. Singapore. January 20-23, 2014. pp. 213-218. DOI PDF

  9. Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo and Cristina Silvano. “Variation Aware Voltage Island Formation for Power Efficient Near-Threshold Manycore Architectures”, In Proceedings of ASP-DAC 2014, 19th Asia and South Pacific Design Automation Conference. Singapore. January 20-23, 2014. pp. 304-310. DOI PDF

2013

  1. Amir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo and Cristina Silvano " A Framework for Compiler Level Statistical Analysis over Customized VLIW Architecture ", In VLSI-SoC 2013 - International Conference on Very Large Scale Integration and System-on-Chip Istanbul, Turkey. 7-9 October 2013, pp. 124-129, DOI PDF

  2. Giovanni Mariani, Vlad-Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Giacomo Marchiri, Cristina Silvano and Koen Bertels. "Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction ", In FPL 2013 - 23rd International Conference on Field Programmable Logic and Applications. Porto, Portugal. 2-4 September 2013. pp. 1-8, DOI PDF

  3. Sotirios Xydis, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. "A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization", In DATE 2013 - International Conference on Design, Automation and Test in Europe. Grenoble, France. March 18-22, 2013, pp. 659-664. url PDF

  4. Edoardo Paone, Nazanin Vahabi, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley, "Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models", In DATE 2013 - International Conference on Design, Automation and Test in Europe. Grenoble, France. March 18-22, 2013, pp. 671-676. url PDF

  5. Sotirios Xydis, Gianluca Palermo, Cristina Silvano. "Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors", In DATE 2013 - International Conference on Design, Automation and Test in Europe. Grenoble, France. March 18-22, 2013, pp. 1649-1654. url  PDF

2012

  1. Edoardo Paone, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou and Thierry Lepley, "An Exploration Methodology for a Customizable OpenCL Stereo-Matching Application Targeted to an Industrial Multi-Cluster Architecture", in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS 2012, 7-12 October 2012, Tampere, Finland. Pp. 503-512, ACM, New York, USA, ISBN: 978-1-4503-1426-8, url PDF

  2. Debora Matos, Gianluca Palermo, Cezar Reinbrecht, Cristina Silvano, Altamiro Amadeu Susin, Luigi Carro. "Floorplan-Aware Hierarchical NoC Topology with GALS Interfaces "In Proceedings of ISCAS 2012 - IEEE International Symposium on Circuits and Systems. Seoul, Korea. 20-23 May 2012, pp. 652-655. ISBN: 9781467302197, ISSN: 0271-4302, url PDF

  3. Giovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Koen Bertels. "Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures", In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2012). Dresden, Germany. 12-16 March 2012, pp. 1379-1384, ISBN: 978-1-4577-2145-8, url   PDF

  4. Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. "Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework. ", In ARCS 2012 Workshops, 2PARMA Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures. Munich, Germany. February 2012 pp. 363-374. url PDF

2011

  1. Debora Matos, Gianluca Palermo, Vittorio Zaccaria, Cezar Reinbrecht, Altamiro Susin, Cristina Silvano and Luigi Carro, "Floorplanning-Aware Design Space Exploration for Application-Specific Hierarchical Networks on-Chip", In NoCArc'11 - Fourth International Workshop on Network on-Chip Architectures. In conjunction with the 44th Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-44) December 3-7, 2011 Porto Alegre, Brazil, ISBN: 9781450309479, doi: 10.1145/2076501.2076508 url PDF

  2. Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Gianluca Palermo, Cristina Silvano. "Two-levels of adaptive buffer for virtual channel router in NoCs", In Proceedings of IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC 2011), Kowloon, Hong Kong, China, October 3-5, 2011, pp. 302-307. ISBN: 978-1-4577-0171-9 DOI: 10.1109/VLSISoC.2011.6081596 url PDF

  3. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems" In Proceedings of the IEEE 9th Symposium on Application Specific Processors (SASP2011), San Diego, CA, USA, 5-6 June 2011, pp. 86-93. IEEE Computer Society, Washington, DC, USA, ISBN: 9781457712128, DOI: 10.1109/SASP.2011.5941085, url PDF

2010

  1. Leandro Fiorin, Gianluca Palermo, Cristina Silvano. "A Monitoring System for NoCs ", in Proceedings of the Third International Workshop on Network on Chip Architectures, NoCArc '10, 2010, ISBN 978-1-4503-0397-2, Atlanta, Georgia, pp. 25--30. In Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43, ACM, New York, NY, USA, 25-30. DOI=10.1145/1921249.1921257 PDF

  2. Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Aleksandar Brankovic, Jovana Jovic, Cristina Silvano. "A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip ", In Proceedings of the 47th Design Automation Conference. Design Automation Conference (DAC-47), Anaheim, CA, USA, 13-18 June 2010, pp. 120-125, New York, NY, USA, ACM/IEEE , ISBN: 9781450300025, doi: 10.1145/1837274.1837307 PDF

  3. Giovanni Mariani, Vittorio Zaccaria, Gianluca Palermo, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Cristina Silvano. " An industrial design space exploration framework for supporting run-time resource management on multi-core systems ", In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2010). Dresden, Germany. March 2010, pp. 196-201. EDAA, Leuven, Belgium, Belgium, ISBN: 978-1-4244-7054-9, url PDF

  4. Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian Vintan, Cristina Silvano. " Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions ", In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2010). Dresden, Germany. March 2010, pp. 271-274. EDAA, Leuven, Belgium, Belgium, ISBN: 978-1-4244-7054-9, url PDF

  5. Vittorio Zaccaria, Gianluca Palermo, Giovanni Mariani, Fabrizio Castro, Cristina Silvano. "Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors ", In ARCS2010 Workshops, PARMA Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, co-located with ARCS 2010, Hannover, Germany, February 2010, pp. 325-331. VDE Verlag, ISBN: 978-3-8007-3222-7 url PDF

2009

  1. Anirban Dutta Choudhury, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria. "Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips ", In NoCArc'09 - Second International Workshop on Network on-Chip Architectures, in Conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-42, New York City, USA, December 2009, pp. 37-42. PDF

  2. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip ", In Euromicro Proceedings of DSD'09 - Conference on Digital System Design. Patras, Greece, August 2009, pp. 383-389. ISBN: 9780769537825, DOI: 10.1109/DSD.2009.154

  3. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors Systems-on-Chip", In Proceedings of the IEEE 7th Symposium on Application Specific Processors, SASP 2009, Co-located with DAC 2009, San Francisco, CA, USA, 27-28 July 2009, pp. 21-28, ISBN: 978-1-4244-4939-2, DOI: 10.1109/SASP.2009.5226331 PDF

  4. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques", In Proceedings of IC-SAMOS'09 – IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July 2009, pp. 118-124. ISBN: 9781424445011, doi: 10.1109/ICSAMOS.2009.5289222. PDF

  5. Leandro Fiorin, Gianluca Palermo, Cristina Silvano. "MPSoCs Run-Time Monitoring through Networks-on-Chip", In DATE 2009 - International Conference on Design, Automation and Test in Europe. Nice, France. April 2009, pp. 558-561. ISBN: 9781424437818. PDF

  6. G. Palermo C. Silvano, V. Zaccaria, "Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures". In Proceedings of ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference. Yokohama, Japan, January 2009, pp. 323-328. ISBN: 9781424427482, DOI: 10.1109/ASPDAC.2009.4796501. PDF

2008

  1. L. Fiorin, G. Palermo, C. Silvano, "A Security Monitoring Service for NoCs", In ACM Proceedings of CODES+ISSS 2008 - International Conference on Hardware-Software Codesign and System Synthesis. Atlanta, Georgia, USA, October 2008, pp. 197-2002. PDF

  2. G. Palermo, C. Silvano, V. Zaccaria, "Robust Optimization of SoC Architectures: A Multi-Scenario Approach", In Proceedings of ESTIMedia 2008 - IEEE Workshop on Embedded Systems for Real-Time Multimedia. Atlanta, Georgia, USA, October 2008, pp. 7-12. PDF

  3. O. Villa, G. Palermo, C. Silvano, "Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures", In Proceedings of CASES 2008 - International Conference on Compilers, Architectures and Synthesis for Embedded Systems. Atlanta, Georgia, USA, October 2008, pp. 81-90. PDF

  4. G. Mariani, G.Palermo, C. Silvano and V. Zaccaria, "An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks", IFIP-VLSI-SOC 2008, 2008 IFIP International Conference on Very Large Scale Integration, 13-15 Oct. 2008, Rhodos (Greece).

  5. G. Palermo, C. Silvano and V. Zaccaria, "Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration", Proceedings of 11th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2008, 2008, Sept. 2-5, Parma, Italy. PDF

  6. M. Monchiero, G. Palermo, C. Silvano, O. Villa, "A Modular Approach to Model Heterogeneous MPSoC at Cycle Level", Proceedings of 11th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2008), 2008, Sept. 2-5, Parma, Italy. PDF

  7. G. Palermo, C. Silvano e V. Zaccaria, "An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods", SAMOS VIII: International Symposium on Systems, Architectures, MOdeling and Simulation, Samos, Greece, July 21-24, 2008. PDF

  8. G. Palermo, C. Silvano e V. Zaccaria, "An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints", IEEE Symposium on Application Specific Processors (SASP 2008), Co-located with DAC 2008, 8-9 June 2008, Anaheim (CA - USA), pp.75-82. PDF

  9. Martino Sykora, Giovanni Agosta and Cristina Silvano, “Dynamic Configuration of Application-Specific Implicit Instructions for Embedded Pipelined Processors”, pp. 1509-1516, in Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008. ISBN: 978-1-59593-753-7, Roger L. Wainwright and Hisham Haddad (Editors) DOI: 10.1145/1363686.1364040 ACM BEST PAPER AWARD SAC2008 - Applications Theme. PDF

2007

  1. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "A Topology Design Customization Approach for STNoC", In Proceedings of NanoNets'07 - International Conference on NanoNetworks. Catania, Italy, September 2007.

  2. L. Fiorin, G. Palermo, S. Lukovic, C. Silvano, "A Data Protection Unit for NoC-based Architectures", CODES+ISSS '07: Proceedings of the 5th IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis, Salzburg, Austria, 2007, pp. 167--172. PDF

  3. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "Application-Specific Topology Design Customization for STNoC", Proceedings of 10th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, Lübeck, Germany, pp. 547-550.  PDF

  4. Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami, "Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations", Proceedings of 10th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, Lübeck, Germany, pp. 539-542. PDF

  5. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "Mapping and Topology Customization Approaches for Application-Specific STNoC Designs", In Proc. of ASAP'07 - 18th IEEE International Conference on Application-specific Systems, Architectures and Processors. Montréal, Québec, Canada, July 2007, pp. 61-68. PDF

2006

  1. G. Beltrame, D. Bruschi, D. Sciuto, C. Silvano, "Decision-theoretic Exploration of Multi-Processor Platforms", CODES+ISSS 2006, in Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006, pp. 205-210, ACM, New York, NY, USA, ISBN: 1-59593-370-0, DOI: 10.1145/1176254.1176305 PDF

  2. Beltrame G., Sciuto D., Silvano C., Paulin P., Bensoudane E., "An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures" IFIP-VLSI-SOC 2006, 2006 IFIP International Conference on Very Large Scale Integration, Publication Date: 16-18 Oct. 2006 On page(s): 146-151 ISBN: 3-901882-19-7; DOI:        10.1109/VLSISOC.2006.313219 url PDF

  3. M. Monchiero, G. Palermo, C. Silvano, O. Villa, "Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors" IC-SAMOS VI Conference - Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos (Greece), July 17 - 20, 2006, pp. 144-151. PDF

  4. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa, "Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs", Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 606-611. Georges G. E. Gielen Editor, European Design and Automation Association Publisher, Leuven, Belgium, ISBN: 3-9810801-0-6; DOI: 10.1145/1131653 PDF

  5. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard and Chuck Pilkington, "Exploiting TLM and Object Introspection for System-Level Simulation", Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 100-105. Georges G. E. Gielen Editor, European Design and Automation Association Publisher, Leuven, Belgium, ISBN: 3-9810801-0-6; DOI: 10.1145/1131515 PDF

2004

  1. G. Beltrame, G. Palermo, D. Sciuto, C. Silvano, “Plug-in of Power Models in the StepNP  Exploration Platform: Analysis of Power/Performance Trade-offs”, Proceedings of the 2004 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2004), Washington DC, USA, 22-25 September, 2004, pp. 85-92, ISBN:1-58113-890-3, DOI: 10.1145/1023833.1023847 PDF

  2. G. Palermo, C. Silvano, “PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures”, Proc. of PATMOS 2004: 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, 15-17 September, 2004, Lecture Notes in Computer Science, Springer, Vol. 3254, 2004, ISBN 978-3-540-23095-3, pp. 521-531. DOI: 10.1007/978-3-540-30205-6_54 PDF

  3. M. Monchiero, G. Palermo, M. Sami, C. Silvano, V. Zaccaria, R. Zafalon, "Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors", GLS-VLSI'04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26--28, 2004, Boston, MA, USA, pp. 440-443. PDF

  4. G. Agosta, G. Palermo, C. Silvano, “Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems”. In SAC04: Proceedings of the 2004 ACM Symposium on Applied Computing, 14-17 March 2004, Nicosia, Cyprus, pp. 891-896, ISBN:1-58113-812-1. PDF

2003

  1. G. Palermo, C. Silvano, V. Zaccaria, ”A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems” Proc. of PATMOS 2003: 13th International Workshop on Power and Timing Modeling, Optimization and Simulation,  September 10-12, 2003, Torino, Italy, Lecture Notes in Computer Science, Springer, Volume 2799, 2003, ISBN: 978-3-540-20074-1, pp. pp. 249 – 258. PDF

  2. G. Palermo, M. Sami, C. Silvano, V. Zaccaria, R. Zafalon, ”Branch Prediction Techniques for Low-Power VLIW Processors”, GLS-VLSI'03: Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 28--29, 2003, Washington, DC, USA, pp. 225-228, ISBN:1-58113-677-3. PDF

  3. G. Palermo, C. Silvano, S. Valsecchi, V. Zaccaria, ”A System-Level Methodology for Fast Multi-Objective Design Space Exploration”, GLS-VLSI'03: Proceedings of the April 28--29, 2003, Washington, DC, USA, pp. 92-95, ISBN:1-58113-677-3. PDF

  4. L. Salvemini, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon, ”A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems” SAC03: Proceedings of the 2003 ACM Symposium on Applied Computing, 9-12 March 2003, Melbourne, Florida, USA, pp. 672-678, ISBN:1-58113-624-2 PDF

  5. G. Palermo, C. Silvano, V. Zaccaria, ”Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture”, DATE 2003: Design, Automation and Test in Europe, Conference and Exhibition, 03–07 Marzo 2003, Munich, GERMANY, Pages: 182-187 suppl. PDF

2002

  1. A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, "Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering", DAC2002 - ACM/IEEE Design Automation Conference, 10-14 June, 2002, New Orleans, USA, Pages: 886-891.   PDF

  2. A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, “An instruction-level methodology for power estimation and optimization of embedded VLIW cores”, Proc. of DATE 2002: ACM/IEEE Design Automation and Test in Europe, Conference and Exhibition, 4-8 March, 2002, p. 1128. PDF

2001

  1. L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, and R. Zafalon, “A Power Modeling and Estimation Framework for VLIW-based Embedded Systems”, Proc. of PATMOS01- IEEE Eleventh International Workshop on Power and Timing Modeling, Optimization and Simulation, Sept. 26-28, 2001, Yverdon-les-Bains, CH. This paper has been selected to be re-published on: ST Journal of System Research, No. 0, July 2003, Art. 5, pp. 52-60.

  2. W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, “Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics”, ISCAS2001: IEEE Int. Symposium on Circuits and Systems, Sydney, Australia, May 5-7, 2001, pp.502-505, vol.4. PDF

  3. W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, “A Design Framework to Efficiently Explore Energy-Delay Tradeoffs”, CODES-2001: 9th ACM/IEEE International Symposium on Hardware/Software Co-Design (Former Workshop), Copenhagen (Danmark), Apr. 25-27, 2001, pp. 260-265. PDF

  4. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, “ Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors”,  DATE2001: IEEE Design, Automation and Test Conference in Europe, Munich, Germany, Mar. 13-16, 2001, pp. 252-257. PDF

2000

  1. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, “Power Exploration for Embedded VLIW Architectures”, ICCAD-2000: IEEE/ACM Int. Conference on Computer Aided Design, San Jose, CA, Nov. 5-9, 2000, pp. 498-503. PDF

  2. P. Bacchetta, L. Daldoss, D. Sciuto, C. Silvano, “Low-Power State Assignment Techniques for Finite State Machines”, ISCAS2000: IEEE Int. Symposium on Circuits and Systems, Geneva (Swizerland), May 28-31, 2000, pp. 641-644, Vol. 2. PDF

  3. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, “Instruction-Level Power Estimation for Embedded VLIW Cores”, CODES-2000: 8th ACM/IEEE International Workshop on Hardware/Software Co-Design, San Diego, CA, May 3-5, 2000, pp. 34-38. PDF

  4. W. Fornaciari, M. Polentarutti, D. Sciuto, C. Silvano, “Power Optimization of System-Level Address Buses based on Software Profiling”, CODES-2000: 8th ACM/IEEE International Workshop on Hardware/Software Co-Design, San Diego, CA, May 3-5, 2000, pp. 29-33. PDF

1999

  1. W. Fornaciari, D. Sciuto, C. Silvano, “Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study”, IEEE International Conference on Computer Design, ICCD-99, Austin, TX (USA), Oct. 10-13, 1999, pp. 131-136. DOI: 10.1109/ICCD.1999.808417 url PDF

  2. W. Fornaciari, D. Sciuto, C. Silvano, “Power Estimation for Architectural Exploration of HW/SW Communication on System-Level Buses”, Proceedings of the Seventh International Workshop on Hardware/Software Co-Design, CODES-99, Rome, Italy, 3-5 May, 1999, pp. 152-156. DOI: 10.1145/301177.301516   PDF

  3. W. Fornaciari, D. Sciuto, C. Silvano, “Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems”, DATE-99: Proceedings of 1999 IEEE Conference on Design, Automation and Test in Europe, Munich (Germany), Mar. 9-12, 1999, pp. 762-763. DOI: 10.1109/DATE.1999.761219 PDF

  4. C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello, R. Scarsi, C. Silvano, R. Zafalon, “RTL Power Embedded Estimation in a Industrial Design Flow”, IEEE Alessandro Volta Memorial Workshop on Low-Power Design, Como, Italy, Mar. 4-5, 1999, pp. 91-96. ISBN: 0-7695-0019-6 url: http://dl.acm.org/citation.cfm?id=832287.835654 PDF

1998

  1. D. Sciuto, C. Silvano, R. Stefanelli, “Systematic AUED Codes for Self-Checking Architectures”, DFT-98: 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Austin, TX (USA), Nov. 2-4, 1998, pp. 183-191. PDF

  2. N. Dragone, C. Guardiani, C. Silvano, R. Zafalon, “Power Invariant Vector Compaction based on Bit Clustering and Temporal Partitioning”, ISLPED 1998, IEEE International Symposium on Low-Power Electronics and Design, Monterey, CA (USA), Aug. 1998, pp. 118-120. ISBN 1-58113-059-7,DOI: 10.1145/280756.280819 PDF

  3. L. Daldoss, D. Sciuto, C. Silvano, “State Encoding for Low Power Embedded Controllers”, ISCAS-98: Proceedings of 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA (USA), May 31 – Jun. 3, 1998, pp. 421-424, Vol. 2. ISBN: 0-7803-4455-3 DOI: 10.1109/ISCAS.1998.706966 PDF

  4. L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Address Bus Encoding Techniques for System-Level Power Optimization”, DATE-98: IEEE Design, Automation and Test in Europe, Conference an Exhibition 1998, Paris (France), Feb. 23-26, 1998, IEEE Computer Society, ISBN: 0-8186-8359-7 pp. 861-866. DOI: 10.1109/DATE.1998.655959 PDF
    In 2008, this paper has been recognized as one of the most influential papers of the past ten years DATE and then selected to be re-published as a chapter of the volume: "Design, Automation, and Test in Europe - The Most Influential Papers of 10 Years DATE" Lauwereins, Rudy; Madsen, Jan (Eds.), 2008, Approx. 250 p., ISBN: 978-1-4020-6487-6, Springer Ed.

1997

  1. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “System-level Power Evaluation Metrics”, ISIS-97: Second Annual IEEE International Conference on Innovative Systems in Silicon, Austin, TX (USA), Oct. 8-10, 1997, pp. 323-330. DOI: 10.1109/ICISS.1997.630275 PDF

  2. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “High-Level Power Estimation of VLSI Systems”, ISCAS-97: Proceedings of 1997 IEEE International Symposium on Circuits and Systems, Hong Kong, Jun. 9-12, 1997, pp. 1804-1807, Vol.3. ISBN: 0-7803-3583-X DOI: 10.1109/ISCAS.1997.621496 PDF

  3. L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems”, in GLS-VLSI-97: Proceedings of Seventh Great Lakes Symposium on VLSI, 1997, Urbana-Champaign, IL (USA), March 13-15, 1997, pp. 77-82, IEEE Computer Society, ISBN: 0-8186-7904-2 DOI: 10.1109/GLSV.1997.580414 PDF
    Citation count: 321. This paper represents my top ranked paper in terms of citations based on Google Scholar.

1996

  1. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “A Conceptual Analysis Framework for Low Power Design of Embedded Systems”, ISIS-96: 1996 Annual IEEE International Conference on Innovative Systems in Silicon (Previously: International Conference on Wafer Scale Integration), Austin, TX (USA), Oct. 9-11, 1996, pp. 170-179. DOI: 10.1109/ICISS.1996.552424 PDF

1995

  1. L. Penzo, D. Sciuto, C. Silvano, “GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications”, ISCAS-95: IEEE International Symposium on Circuits and Systems, Seattle, WA (USA), Apr. 29 – May 3, 1995, pp. 912-915.

  2. L. Penzo, D. Sciuto, C. Silvano, “VLSI Design of Systematic Odd-Weight-Column Byte Error Detecting SEC-DED Codes”, VLSI Design 95: IEEE 8th International Conference on VLSI Design, New Delhi (India), Jan. 4-7, 1995, pp. 156-160. DOI: 10.1109/ICVD.1995.512096 url

1992

  1. L. Populin, G. Sada, C. Silvano, “RamGen: a Dual Port Static RAM Generator”, ASIC-92: Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit, Rochester, NY (USA), 21-25 Sept., 1992, pp. 509-512, DOI: 10.1109/ASIC.1992.270211

1991

  1. F. Bozzetti, C. Silvano, "Architecture and Design Methodology of a 32-bit Microprocessor”, Proc. of COMPEURO-91: Advanced Computer Technology, Reliable Systems and Applications, 5th Annual European Computer Conference Bologna (Italy), 13-16 May, 1991, pp. 613-617. DOI: 10.1109/CMPEUR.1991.257460