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CRISTINA SILVANO

Link to CV (July 2014)

Link to Cristina Silvano's Publications

Link to Cristina Silvano on DBLP

Link to Cristina Silvano's Google Scholar Citations

CV SUMMARY

Current Position and Academic Career

I am currently Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), System Architectures Group. In December 2013, I have received the Scientific National Qualification in Italy as Full Professor in sector 09/H1 Information Processing Systems and in sector 01/B1 Informatics  (as defined in DD222 of July 20, 2012). From 2006, I am also collaborating with ALaRI-Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH).  From 2000 to 2002, I was Assistant Professor in Computer Science at University of Milan, Department of Computer Science. From 1999 to 2000, I was Post-Doctoral Researcher at Politecnico di Milano, mainly working on the research project: “Power estimation methodologies for VLIW architectures”, in collaboration with STMicroelectronics. From 1998 to 1999, I was Post-Doctoral Researcher in the Electronic Design Automation Area at CEFRIEL (Center for the Research and the Education in Information Engineering) in Milan. From March 1996 to October 1998, I was Ph.D. Student at Università degli Studi di Brescia (Italy). I have received the Ph. D. Degree in Computer Engineering on March 1999 discussing my thesis titled: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems”. (Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).

Industrial Career

From May 1987 to February 1996, I was with the R&D Laboratories of Group Bull (also known as Bull HN Information Systems), Pregnana Milanese (Italy), where I held the position of Design Engineer up to March 1993 and Senior Design Engineer up to February 1996. During this period, I was also Visiting Engineer at Bull R&D Labs, Billerica (MA - USA) in Fall 1988 and in Spring 1989. I also was Visiting Engineer at VLSI Technology Inc., Munich (Germany) in February-March 1990, and at VLSI Technology Inc. in S. José (CA-USA) in April 1990. From 1992, I was part of the Bull-IBM (Austin-US) design team for the design of the first multiprocessor system based on IBM PowerPC processor architecture. These shared-memory multiprocessor systems have been fully designed in the Bull R&D Labs in Italy and then commercialized as Bull Escala UNIX Servers and as IBM RS/6000 Symmetric Multiprocessor Servers. During this project, I was Visiting Engineer at IBM Somerset Design Center, Austin (TX - USA) in Fall 1993 and in Spring 1994.

 

Education

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Laurea Degree (M. Sc.) in Electrical Engineering from Politecnico di Milano (Italy) in 1987, (Final grade 100/100). MS Thesis on: “Theorical and numerical study of shallow waters fludodynamic models”, Advisor: Prof. G. Prouse, Politecnico di Milano (Co-Advisor Prof. L. Gotusso, Politecnico di Milano).

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Ph. D. Degree in Computer Engineering from University of Brescia (Italy) on March 1999, Ph.D. Thesis title: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems” (Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).

Research Activities

My research focuses on Computer Architecture and Electronic Design Automation, with particular emphasis on power-aware design and design space exploration of embedded architectures, adaptive design and monitoring of applications for many-core architectures, many-core architectures based on Networks-on-Chip, technology-aware many-core architectures and fault tolerant coding techniques. Highlights of my recent research can be found in the following five research papers: ACM Trans. on Embedded Computing Systems 2013 [J2], ACM Trans. on Embedded Computing Systems 2012 [J5], IEEE Trans. on CAD 2009 [J8], IEEE Trans. on Computers 2008 [J9], IEEE Trans. on VLSI Systems 2006 [J13].

Research Projects and International Collaborations

My research activities have been carried out in collaboration with several international universities, research centers and industries (about 90 out of my 140 scientific publications include co-authors with different affiliations, 35 out of them with industrial co-authors, 106 co-authors overall). My research has been funded by several national and EU projects selected based on a competitive process. Since 2003 I was co-applicant and active participant of 7 European and 2 industrially funded projects (attracting around 3.5 M€ funding for POLIMI). Among them, I was Project Coordinator of two European projects: FP7-2PARMA (2010-2013)  on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures" and previously FP7-MULTICUBE (2008-2010) on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications". Since 1996 I have started a continuous research collaboration with STMicroelectronics and I was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008).

Scientific Outcomes

My scientific production consists of more than 140 scientific publications:

 

-     Co-author of 25 top-ranked journal publications (including 14 IEEE/ACM Transactions: 5 IEEE Trans. on VLSI Systems, 4 IEEE Trans. on CAD, 3 ACM Trans. on Embedded Computing Systems, 1 IEEE Trans. on Computers, 1 IEEE Trans. on Information Theory);

-     Co-author of 13 chapters in scientific books;

-     Co-author of more than 90 scientific publications on peer-reviewed conferences/workshops including 31 top-level conferences (15 DATE, 8 CODES-ISSS, 3 ASP-DAC, 2 DAC, 2 CASES and 1 ICCAD) collecting one Best Paper Award, one HiPEAC paper award and one of the most influential papers published at DATE conference in the decade 1998-2008;

-    Co-author of the scientific book: “Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems”, Kluwer Academic Publisher (2003);

-    Co-author of the academic textbook (in Italian): “Progettazione Digitale” (Logic Design), McGraw-Hill (2002, 2007);

  Co-editor of 2 scientific books: “Low-Power Networks-on-Chip”, Springer (2010) and “Multi-objective design space exploration of multiprocessor SoC architectures”, Springer (2011);

-   Inventor/Co-inventor of 11 patent applications with Group Bull or STMicroelectronics (7 out of 11 already granted).

 

Based on Google Scholar (31/7/2014), my h-index is 25, my i10-index is 55 and my total number of citations is 2182 (my top ranked paper has been published in 1997 collecting up to 284 citations). 

 

Scientific Services

I am an active contributor to the scientific community and I regularly serve as Member (or Track Chair) of the Program Committee of several top-level conferences such as DAC, DATE, NOCS, HPCA, MICRO, ASAP, FPL. I was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. I was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). I have also organized 12 international workshops as Program or General Chair. I was Guest Co-Editor of two special issues on journals and Subject Area Editor of the Journal of System Architecture (Elsevier). I am Senior Member of IEEE (since 2009) and Member of HiPEAC Network of Excellence.

 

Evaluator of Research Projects for Various Science Foundations

I have been invited by the European Commission as Independent Expert to review several projects such as ARTEMIS JU Project 295440 PaPP (Portable and Predictable Performance on heterogeneous embedded many-cores), the FP7 STREP Project 288570 ParaPhrase (Parallel Patterns for Adaptive Heterogeneous Multicore Systems) and the FP7 STREP project 248976-REFLECT (Rendering FPGAs to Multi-Core Embedded Computing). From 2010 to 2012, she has been called from the European Commission as Independent Expert to evaluate proposals submitted to the EC "Future and Emerging Technologies" programme (EC FET-Open) on FP7-ICT-2009 Information and Communication Technologies. In 2010, she has been called as Reviewer of research proposals submitted to Programme Blanc International Edition 2010,  ANR (Agence Nationale de la Recherche), France. From 2005 to 2008, she has been called from the European Commission as Independent Expert to review the Network-of-Excellence project FP6 - IST-4408 HiPEAC (High-Performance Embedded Architectures and Compilers). In April 2005, she has been called from the European Commission as Independent Expert to evaluate project proposals submitted to the IV Call IST (Information Society Technology) - FP6 (6th Framework Programme) on Nanoelectronics. In 2007, she has been called as Primary Evaluator for research projects at INRIA (French National Institute for Computer Science,- France). In 2008 she has been invited as Member of the Review Panel for Computer Science,  Academy of Finland, Research Council for Natural Sciences and Engineering. In 2009 she has been invited as Chair of the same review panel.

Recent Invited Talks, Seminars and Panels

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May 15th, 2014, "Managing Adaptability in Dynamically Reconfigurable Architectures through Performance Monitoring and Prediction", Talk at the Thematic Section on Reconfigurable, HiPEAC Computing System Week, Barcelona, Host: Georgi Gaydadjiev, Professor, Chalmers University of Technology, Sweden.
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Sep. 4th, 2013, Panel Moderator on: “EU Horizon 2020 on Reconfigurable Computing” Invited Speakers: Panos Tsarchopoulos, Future and Emerging Technologies, EU Project Officer; Georgi Kuzmanov, ARTEMIS Joint Undertaking, EU Programme Officer; held at FPL2013, 23rd International Conference on Field Programmable Logic and Applications, Porto
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June 8th, 2012, “Automatic Design Space Exploration for Multi-core Architectures”, Talk at Intel Labs, Santa Clara (USA), Host: Dr. Akhilesh Kumar, Intel.

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February 7th, 2012, "Design Space Exploration and Run-time Resource Management for Multi-core Architectures", Talk at The University of Texas at Austin (USA), Electrical and Computer Engineering, Computer Architecture Seminar Series, Austin, Host: Yale Patt, Professor, University of Texas at Austin.

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April 7th, 2011, "2PARMA Project: PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures", HIPEAC Cluster Meeting on Multi-core Architectures, 2011 Chamonix (F), Host: Per Stenström, Professor, Chalmers University of Technology, Sweden.

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November 24th, 2010, "Automatic Design Space Exploration for Chip Multi-processors", Workshop on  "Challenges in Embedded System Design": Involvement of SMEs in Designing Complex Systems (CMM 2010), University of Lugano, Switzerland, Workshop Organizers: G. De Micheli (EPFL) and M. Sami (USI-Politecnico di Milano).

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July 6th, 2010, "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", Research Projects Workshop at ISVLSI 2010: IEEE Computer Society Annual Symposium on VLSI, July 5-7, 2010, Lixouri Kefalonia, Greece.

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June 18th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California, Riverside, CA, USA,  "Automatic Design Space Exploration for Chip-Multi Processors" (Slides). Host: Walid Najjar, Professor, Computer Science and Engineering, University of California Riverside.

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June 17th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California, Irvine, CA, USA,  "Automatic Design Space Exploration for Chip-Multi Processors" (Slides). Host: Alexander V. Veidenbaum, Professor, Dept. of Computer Science, University of California Irvine.

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March 23rd, 2010, at 10:30 am in Room HB 16.140, Delft Technical University, Computer Engineering Colloquium Series. Title of the talk: "A Design Space Exploration Framework for Run-Time Resource Management on Multi-Core Architectures"   (Slides). Host: Prof. Koen Bertels, Delft Technical University (NL).

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December 17, 2009, 11:15-12:00, Location: 3B00, NEC Laboratories America, Inc., Princeton Campus, Princeton (NJ - USA), Title of the talk: "Automatic Design Space Exploration for Chip-Multi Processors". Host: Dr. Marcello Lajolo (NEC Laboratories America).

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December 16, 2009, 4:45pm, E-Quad, B327, Princeton University, Department of Electrical Engineering, Computer Engineering Seminar, Title of the Seminar: "Automatic Design Space Exploration for Chip-Multi Processors", Host: Prof. Ruby Lee, Princeton University. (Announcement).

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July 29th, 2009, 11am-12pm PT Location: Kappa, 1U, HP Labs, Palo Alto, Title of the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs", Host: Dr. Matteo Monchiero (Exascale Computing Lab, HP Labs, Palo Alto). 

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May 14th,2009,  at 16h00 in Room HB 16.140, Delft Technical University, Computer Engineering Colloquium Series. Title of the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs" (Slides). Host: Prof. Koen Bertels, Delft Technical University (NL).

 

Academic Services

I have balanced my effort in teaching at Undergraduate and M.Sc. level. I annually teach basic courses on Computer Architectures and Operating Systems and M.Sc. courses on Advanced Computer Architectures. I enjoy teaching and I have an extensive English-speaking teaching experience in a multi-cultural environment at Como Campus of Politecnico di Milano and more recently at Università della Svizzera Italiana (USI). I am an active contributor to the organisation of teaching activities and tracks in Computer Engineering at POLIMI, mainly at Como Campus, where I am responsible for the Committee for the evaluation of undergrate study plans and I am participating to the Committee on teaching, the Committee on graduate admissions and the Committee on undergraduate transfers. I was advisor of 60+ M.Sc. students and advisor/co-advisor of 7 Ph.D. students. Currently, I am advisor of 3 Ph.D. students and my research staff is composed of two faculty members and two Post-doc researchers.

 

Ph.D. STUDENTS SUPERVISION:


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VITTORIO ZACCARIA, Ph. D., currently Assistant Professor at DEIB, Politecnico di Milano, System Architectures Group. First employment: R&D Engineer at STMicroelectronics in Agrate B. (I) and Manno (CH). Ph.D. Thesis on: "Power exploration methodologies for VLIW-based systems", XIV Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2002, Advisor: prof. M. Sami. Co-Advisors: prof. D. Sciuto, Dr. C. Silvano


2

GIANLUCA PALERMO, Ph.D., currently Assistant Professor at DEIB, Politecnico di Milano, System Architectures Group. First employment: Post-Doc at DEI, Politecnico di Milano. Ph.D. Thesis on: "Design Methodologies for Embedded Architectures based on Network on-Chip", XVIII Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2006, Advisor: prof. C. Silvano


3

GIOVANNI BELTRAME, currently Assistant Professor at École Polytechnique de Montréal. First employment: Microelectronics Engineer at European Space Agency (NL). XVIII Ph.D. cycle at Politecnico di Milano, Ph.D. Thesis on “Modeling, Simulating, Analysis and Optimization of Multi-Processor System-on-Chip Platforms”, Ph. D. defense: February 2006, Advisor: prof. D. Sciuto. Co-Advisor: prof. C. Silvano.


4

MATTEO MONCHIERO, Ph.D., currently Senior Research Scientist, Intel Labs at Santa Clara (CA, US). First employment: Post Doctoral Research Associate at HP Labs in Palo Alto, Exascale Computing Lab., Ph.D. Thesis on: “Power/performance analysis and optimization of multicore architectures”, XIX Ph.D cycle at Politecnico di Milano, Ph. D. defense: February 2007, Advisor: prof. C. Silvano


5

ORESTE VILLA, Ph.D., currently Senior Research Scientist at NVIDIA (CA, USA). First employment: Research Scientist at the High Performance Computing Group at Pacific Northwest National Laboratory , Richland, WA (USA), Ph.D. Thesis: “Designing and Programming Multi-core Architectures”, XX Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2008, Advisor: prof. C. Silvano


6

GIOVANNI MARIANI, Ph. D., currently Post-Doc in my research group at DEIB, Politecnico di Milano. First employment: Post-Doc at ALaRI, the Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH), Ph.D. Thesis: "A Design Space Exploration Methodology Supporting Run-time Resource Management for Multi-Core Architectures", Ph. D. at Università della Svizzera Italiana (CH), Ph. D. Defense: March, 2011, Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano


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LEANDRO FIORIN, Ph.D., currently Research Scientist at ASTRON & IBM Center of Exascale Computing (NL). First employment: Post-Doc at ALaRI, the Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH), Ph.D. Thesis: "High level services for Networks-on-Chip”, Ph.D. at Università della Svizzera Italiana (CH), Defense: September 2012, Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano. 


8

EDOARDO PAONE, Ph. D. student, XXVII cycle, DEIB, Politecnico di Milano. Ph.D. Thesis: "HW/SW Co-exploration Methodologies for Exploiting Parallelism in Heterogeneous Systems”. Advisor: prof. C. Silvano


9

IOANNIS STAMELAKOS, Ph. D. student, XXVIII cycle, DEIB, Politecnico di Milano. Ph.D. Thesis: “Technology-Aware Many-core Architecture Design”. Advisor: prof. C. Silvano. Co-advisor: prof. G. Palermo.


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AMIR HOSSEIN ASHOURI, Ph. D. student, XXVIII cycle, DEIB, Politecnico di Milano. Ph.D. Thesis: “Compiler/Architecture Co-exploration of Customized VLIW Architectures”. Advisor: prof. C. Silvano.

Visitors

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SOTIRIOS XYDIS, Ph. D. from Technical University of Athens, Post-Doc at DEI, Politecnico di Milano (From Nov. 2011 to July 2013).

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Arpad Gellért, Ph. D., Assistant Professor, “Lucian Blaga” University of Sibiu, Romania, Visiting Researcher, Spring 2009.

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Caroline Concatto, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 15-01-10 to 15-04-10 , FP7 HiPEAC NoE Collaboration Grant.

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Debora Matos, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.

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Anelise Kologeski, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.