CV

CRISTINA SILVANO

Short CV

She is an Associate Professor (with tenure) in Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica e Informazione, System Architectures Group. I annually teach basic and advanced courses on computer architectures and operating systems. She is currently Project Coordinator of the European Project FP7-2PARMA-248716 on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures" (Jan. 2010 - Dec. 2012). Previously she was Project Coordinator of the European Project FP7-MULTICUBE-216693 on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications" (Jan. 2008 - June 2010). She is an active member of the computing and embedded systems design community and I regularly serve in several international program committees. She also organized 15 international conferences and workshops as Program Chair or General Chair.

Her current primary research interests are in the areas of Computer Architectures and Electronic Design Automation, with particular emphasis on design space exploration techniques and low-power design techniques for multi-processor systems-on-chip. She is co-author of more than one hundred scientific publications on peer-reviewed international journals and conferences (including 12 IEEE/ACM Transactions and collecting one Best Paper Award). She is co-author of the scientific book: "Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems", published by Kluwer Academic Publisher (2003). Co-author of two editions of the academic textbook (in Italian): “Progettazione Digitale” published by McGraw-Hill. She is co-editor of the books: "Low-Power Networks-on-Chip", Springer (October 2010), "Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", Springer (2011) and "Run-time Management techniques for Many-core Architectures" to be published by Springer (2013). She is Inventor or co-inventor of 11 international patents (7 out of 11 already granted). She is Senior Member of IEEE and Member of HiPEAC Network of Excellence. Based on Google Scholar (25/02/2013), her h-index is 21 and total number of citations is 1767 (her top ranked paper has been published in 1997 collecting up to 269 citations).

Link to Cristina Silvano's Publications

Link to Cristina Silvano on DBLP

Education

	*Laurea Degree (M. Sc.)* in Electrical Engineering from Politecnico di Milano (Italy) in 1987, (Final grade 100/100). MS Thesis on: “Theorical and numerical study of shallow waters fludodynamic models”, Advisor: Prof. G. Prouse (Co-Advisor Prof. L. Gotusso).
	*Ph. D. Degree* in Computer Engineering from University of Brescia (Italy) on March 1999, Ph.D. Thesis title: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems” (Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).

Career

	From September 2002 to present, she is an Associate Professor (with tenure) in Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica e Informazione. Her current primary research interests are in the areas of Computer Architectures and Electronic Design Automation, with particular emphasis on design space exploration techniques and low-power design techniques for multi-processor systems-on-chip. From 2006, she is also collaborating with ALaRI-Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH).
	From October 2000 to September 2002, she was Assistant Professor in Computer Science at University of Milan, Department of Computer Science.
	From September 1999 to September 2000, she was Post-Doctoral Researcher at the Dipartimento di Elettronica e Informazione, Politecnico di Milano. Her research activities were mainly related to the research contract: “Power estimation methodologies for VLIW architectures”, in collaboration with the Advanced System Technology Division of ST Microelectronics. The research activity carried out aimed at defining a power estimation and optimization methodology for VLIW (Very Long Instruction Word) architectures based on the Lx/ST200 family of VLIW embedded processor cores (developed as a partnership between HP Labs and STMicroelectronics). The ST200 family (including the ST210, ST220, ST231 processor cores) is used today for embedded media processing in a variety of audio, video and imaging consumer products.
	From November 1998 to August 1999, she was a Consultant Researcher in the Electronic Design Automation Area at CEFRIEL (Center for the Research and the Education in Information Engineering) in Milan. The research activity carried out aims at defining a more general HW/SW co-design environment for control dominated embedded systems. This work is part of the co-design project named TOSCA (Tools for System Co-design Automation) and the European Project No. 26796 PEOPLE (Power Estimation for fast exPLoration of Embedded systems).
	From March 1996 to October 1998, she was Ph.D. Student at the Dipartimento di Elettronica per l’Automazione, Università degli Studi di Brescia (Italy). She received the Ph. D. Degree in Computer Engineering on March 1999 discussing her thesis titled: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems”. (Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).
	From May 1987 to February 1996, she was with Groupe Bull (also known as Bull HN Information Systems), where she held the position of Design Engineer up to March 1993 and Senior Design Engineer up to February 1996 in the Research & Development Labs in Pregnana M. (Italy). She participated in the design of several VLSI circuits for Bull computer systems. She has also been involved in the definition of design and simulation methodologies at the system-level. From 1992, she was part of the Bull - IBM (Austin-USA) team for the design of the first multiprocessor systems based on PowerPC processor architecture. These systems have been fully designed in the Bull R&D Labs in Italy and then commercialized as Bull Escala Servers and IBM RS/6000 Symmetric Multiprocessor Servers. These shared-memory multiprocessor systems are symmetric and scalable up to eight processors. The architecture has been designed to support the family of IBM PowerPC processors (PowerPC 601, 604 and 620).

Research Projects

	She participated to a number of national and international research projects. She is currently the Project Coordinator of the European project FP7-2PARMA-248716 on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures" (Jan. 2010 - Dec. 2012). EC Contribution to the project: 2.74 Mio Euro. The 2PARMA Consortium is composed of seven partners: Politecnico di Milano (Italy), STMicroelectronics (Italy and France), Heinrich Hertz Institute - Fraunhofer Institute for Telecommunications (Germany), IMEC (Belgium), ICCS - Institute of Communication and Computer Systems (Greece), RWTH Aachen University (Germany), Synopsys (Belgium). The 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and design space exploration methodologies for Many-core Computing Fabrics.
	She was the Project Coordinator of the European project FP7-MULTICUBE-216693 on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications" (Jan. 2008 - June 2010). EC Contribution to the project: 2.098 Mio Euro. The MULTICUBE Consortium was composed of nine partners: Politecnico di Milano (Italy), Design of Systems on Silicon – DS2 (Spain), STMicroelectronics (Italy), IMEC (Belgium), ESTECO (Italy), University of Lugano - ALaRI (Switzerland), University of Cantabria (Spain), STMicroelectronics Beijing (China), Institute of Computing Technology – Chinese Academy of Sciences (China). In the context of the MULTICUBE project, she is also leading a research group at Politecnico di Milano whose research focuses on design space exploration for multi-processor architectures working on an open-source tool (MULTICUBE Explorer) to enable an automatic and fast optimization of configurable system architectures towards a set of objective functions such as energy and delay. MULTICUBE Explorer provides a set of innovative sampling and optimization techniques to help finding the multi-objective Pareto points. It also provides an open XML interface for supporting exploration of new platforms/architectures by interacting with a system-level simulator.
	She is currently participating to the ARTEMIS SMECY Project on "Smart Multicore Embedded Systems" (start date: 01/02/2010). The SMECY project includes 30 partners from 9 European countries (among others we can cite STMicroelectronics and Thales). Project *Coordinator:* Francois Pacull (CEA, France).
	She is participating to the European Integrated Project COMPLEX - 247999 on "Co-design and power management in platform-based design space exploration" (Dec. 2009 – Nov. 2012). EC Contribution to the project: 4.8 Mio Euro. The COMPLEX project includes 14 partners from 6 countries (including China). Project Coordinator: OFFIS – Germany. Project Partners: Thales Communications SA –France, Synopsys Belgium NV – Belgium, Universidad de Cantabria – Spain, EDALAB Srl –Italy, Magillem Design Services SAS – France, STMicrolectronics Srl – Italy, STMicroelectronics (Beijing) – China, GMV Aerospace and Defence – Spain, Politecnico di Milano – Italy, Politecnico di Torino – Italy, Chipvision Design Systems– Germany, IMEC – Belgium, ECSI – France.
	From 2006 to 2008, she collaborated with ALaRI-Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH) to the research and management activities of the European Research Project MEDEA+ LoMoSA+ (2A708): "Low-power expertise for Mobile & multi-media System Applications". Project Coordinator: NXP Semiconductors (NL). Project partners: STMicroelectronics, Thales, Thomson, DS2, CEA-LETI, CEA-LIST, TIMA, ALaRI, University of Cantabria. Our research activity on a definition of a secure Network-on-Chip architecture has been done in collaboration with STMicroelectronics (Grenoble, F) and it has been the subject of one patent application to the European Patent office, afterwards extended to the USA Dept. of Commerce, Patent and trademark Office (US patent granted in 2012).
	In the past, she was also Principal Investigator in some industrial funded research projects: She was Principal Investigator in the two-year research contract: "Low Power Network on Chip and Multiprocessor Platforms" (2006-2008) between DEI, Politecnico di Milano and Advanced System Technology Division of STMicroelectronics Agrate B. She was Principal Investigator in the two-year research contract: “Low Power Network on Chip and Embedded Architectures”(2003-2005) between DEI, Politecnico di Milano and Advanced System Technology Division of STMicroelectronics Agrate B.

Evaluator of Research Projects for Various Science Foundations

From 2010 to 2012, she has been called from the European Commission as Independent Expert to review the STREP project FP7-248976-REFLECT (Rendering FPGAs to Multi-Core Embedded Computing). In 2010 to 2012, she has been called from the European Commission as Independent Expert to evaluate proposals submitted to the FET-Open programme on FP7-ICT-2009 Information and Communication Technologies. In 2010, she has been called as Reviewer of research proposals submitted to Programme Blanc International Edition 2010, ANR (Agence Nationale de la Recherche), France. From 2005 to 2008, she has been called from the European Commission as Independent Expert to review the Network-of-Excellence project FP6 - IST-4408 HiPEAC (High-Performance Embedded Architectures and Compilers). In April 2005, she has been called from the European Commission as Independent Expert to evaluate project proposals submitted to the IV Call IST (Information Society Technology) - FP6 (6th Framework Programme) on Nanoelectronics. In 2007, she has been called as Primary Evaluator for research projects at INRIA (French National Institute for Computer Science,- France). In 2008 she has been invited as Member of the Review Panel for Computer Science, Academy of Finland, Research Council for Natural Sciences and Engineering. In 2009 she has been invited as Chair of the same review panel.

Recent International Talks and Seminars

	June 8^th, 2012, “Automatic Design Space Exploration for Multi-core Architectures”, Talk at Intel Labs, Santa Clara (USA), Host: Dr. Akhilesh Kumar, Intel.
	February 7th, 2012, "Design Space Exploration and Run-time Resource Management for Multi-core Architectures", Talk at The University of Texas at Austin (USA), Electrical and Computer Engineering, Computer Architecture Seminar Series, Austin, Host: Yale Patt, Professor, University of Texas at Austin.
	April 7th, 2011, "2PARMA Project: PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures", HIPEAC Cluster Meeting on Multi-core Architectures, 2011 Chamonix (F), Host: Per Stenström, Professor, Chalmers University of Technology, Sweden.
	November 24th, 2010, "Automatic Design Space Exploration for Chip Multi-processors", Workshop on "Challenges in Embedded System Design": Involvement of SMEs in Designing Complex Systems (CMM 2010), University of Lugano, Switzerland, Workshop Organizers: G. De Micheli (EPFL) and M. Sami (USI-Politecnico di Milano).
	July 6th, 2010, "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", Research Projects Workshop at ISVLSI 2010: IEEE Computer Society Annual Symposium on VLSI, July 5-7, 2010, Lixouri Kefalonia, Greece.
	June 18th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California, Riverside, CA, USA, "Automatic Design Space Exploration for Chip-Multi Processors" (Slides). Host: Walid Najjar, Professor, Computer Science and Engineering, University of California Riverside.
	June 17th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California, Irvine, CA, USA, "Automatic Design Space Exploration for Chip-Multi Processors" (Slides). Host: Alexander V. Veidenbaum, Professor, Dept. of Computer Science, University of California Irvine.
	March 23rd, 2010, at 10:30 am in Room HB 16.140, Delft Technical University, Computer Engineering Colloquium Series. Title of the talk: "A Design Space Exploration Framework for Run-Time Resource Management on Multi-Core Architectures" (Slides). Host: Prof. Koen Bertels, Delft Technical University (NL).
	December 17, 2009, 11:15-12:00, Location: 3B00, NEC Laboratories America, Inc., Princeton Campus, Princeton (NJ - USA), Title of the talk: "Automatic Design Space Exploration for Chip-Multi Processors". Host: Dr. Marcello Lajolo (NEC Laboratories America).
	December 16, 2009, 4:45pm, E-Quad, B327, Princeton University, Department of Electrical Engineering, Computer Engineering Seminar, Title of the Seminar: "Automatic Design Space Exploration for Chip-Multi Processors", Host: Prof. Ruby Lee, Princeton University. (Announcement).
	July 29th, 2009, 11am-12pm PT Location: Kappa, 1U, HP Labs, Palo Alto, Title of the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs", Host: Dr. Matteo Monchiero (Exascale Computing Lab, HP Labs, Palo Alto).
	May 14th,2009, at 16h00 in Room HB 16.140, Delft Technical University, Computer Engineering Colloquium Series. Title of the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs" (Slides). Host: Prof. Koen Bertels, Delft Technical University (NL).

Ph.D. STUDENTS SUPERVISION:

	VITTORIO ZACCARIA, Ph. D., currently Assistant Professor at DEI, Politecnico di Milano, System Architectures Group. First employment: R&D Engineer at STMicroelectronics in Agrate B. (I) and Manno (CH). Ph.D. Thesis on: "Power exploration methodologies for VLIW-based systems", XIV Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2002, Advisor: prof. M. Sami. Co-Advisors: prof. D. Sciuto, Dr. C. Silvano
	GIANLUCA PALERMO, Ph.D., currently Assistant Professor at Dipartimento di Elettronica e Informazione, Politecnico di Milano, System Architectures Group. First employment: Post-Doc at DEI, Politecnico di Milano. Ph.D. Thesis on: "Design Methodologies for Embedded Architectures based on Network on-Chip", XVIII Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2006, Advisor: prof. C. Silvano
	GIOVANNI BELTRAME, currently Assistant Professor at École Polytechnique de Montréal. First employment: Microelectronics Engineer at European Space Agency (NL). XVIII Ph.D. cycle at Politecnico di Milano, Ph.D. Thesis on “Modeling, Simulating, Analysis and Optimization of Multi-Processor System-on-Chip Platforms”, Ph. D. defense: February 2006, Advisor: prof. D. Sciuto. Co-Advisor: prof. C. Silvano.
	MATTEO MONCHIERO, Ph.D., currently Senior Research Scientist, Intel Labs at Santa Clara (CA, US). First employment: Post Doctoral Research Associate at HP Labs in Palo Alto, Exascale Computing Lab., Ph.D. Thesis on: “Power/performance analysis and optimization of multicore architectures”, XIX Ph.D cycle at Politecnico di Milano, Ph. D. defense: February 2007, Advisor: prof. C. Silvano
	ORESTE VILLA, Ph.D., currently (and first employment): Research Scientist at the High Performance Computing Group at Pacific Northwest National Laboratory , Richland, WA (USA), Ph.D. Thesis: “Designing and Programming Multi-core Architectures”, XX Ph.D. cycle at Politecnico di Milano, Ph. D. defense: February 2008, Advisor: prof. C. Silvano
	GIOVANNI MARIANI, Ph. D., currently (and first employment): Post-Doc at ALaRI, the Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH), Ph.D. Thesis: "A Design Space Exploration Methodology Supporting Run-time Resource Management for Multi-Core Architectures", Ph. D. at Università della Svizzera Italiana (CH), Ph. D. Defense: March, 2011, Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano
	LEANDRO FIORIN, Ph.D., currently (and first employment): Post-Doc at ALaRI, the Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH), Ph.D. Thesis: "High level services for Networks-on-Chip”, Ph.D. at Università della Svizzera Italiana (CH), Defense: September 2012, Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano.
	MARCO CERIANI, Ph. D. student, DEI, Politecnico di Milano.
	EDOARDO PAONE, Ph. D. student, DEI, Politecnico di Milano.
	IOANNIS STAMELAKOS, Ph. D. student, DEI, Politecnico di Milano.
	AMIR HOSSEIN ASHOURI, Ph. D. student, DEI, Politecnico di Milano.

OTHER PReSENt/past Ph.D. STUDENTS and RESEARCH COLLABORATORS:

	GIOVANNI AGOSTA, Ph. D., currently Assistant Professor at DEI, Politecnico di Milano. Formal Languages and Compilers Group. His current research focuses on Dynamic Compilation for ILP Architectures. The research advisor is Prof. Stefano Crespi Reghizzi, Politecnico di Milano.
	SOTIRIOS XYDIS, Ph. D. from Technical University of Athens, currently Post-Doc at DEI, Politecnico di Milano.
	IYAD AL KHATIB, Ph. D. from Royal Institute of Technology, Stockholm, currently Post-Doc at DEI, Politecnico di Milano.
	Arpad Gellért, Ph. D., Assistant Professor, “Lucian Blaga” University of Sibiu, Romania, Visiting Researcher, Spring 2009.
	Caroline Concatto, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 15-01-10 to 15-04-10 , FP7 HiPEAC NoE Collaboration Grant.
	Debora Matos, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.
	Anelise Kologeski, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.