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CRISTINA SILVANO

Link to my CV (Nov. 2014)

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Link to my publications

Link to my publications on DBLP

Link to my citations on Google Scholar

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CV SUMMARY

Current Position and Academic Career

I am currently Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria. In December 2013, I have received the Scientific National Qualification in Italy as Full Professor in sector 09/H1 Information Processing Systems and in sector 01/B1 Informatics  (as defined in DD222 of July 20, 2012). From 2006, I am also collaborating with ALaRI-Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH).  From 2000 to 2002, I was Assistant Professor in Computer Science at University of Milan, Department of Computer Science. From 1999 to 2000, I was Post-Doctoral Researcher at Politecnico di Milano, mainly working on the research project: “Power estimation methodologies for VLIW architectures”, in collaboration with STMicroelectronics. From 1998 to 1999, I was Post-Doctoral Researcher in the Electronic Design Automation Area at CEFRIEL (Center for the Research and the Education in Information Engineering) in Milan. From March 1996 to October 1998, I was Ph.D. Student at Università degli Studi di Brescia (Italy). I have received the Ph. D. Degree in Computer Engineering on March 1999.

Industrial Career

From May 1987 to February 1996, I was with the R&D Laboratories of Group Bull (also known as Bull HN Information Systems), Pregnana Milanese (Italy), where I held the position of Design Engineer up to March 1993 and Senior Design Engineer up to February 1996. During this period, I was also Visiting Engineer at Bull R&D Labs, Billerica (MA - USA) in Fall 1988 and in Spring 1989. I also was Visiting Engineer at VLSI Technology Inc., Munich (Germany) in February-March 1990, and at VLSI Technology Inc. in S. José (CA-USA) in April 1990. From 1992, I was part of the Bull-IBM (Austin-US) design team for the design of the first multiprocessor system based on IBM PowerPC processor architecture. These shared-memory multiprocessor systems have been fully designed in the Bull R&D Labs in Italy and then commercialized as Bull Escala UNIX Servers and as IBM RS/6000 Symmetric Multiprocessor Servers. During this project, I was Visiting Engineer at IBM Somerset Design Center, Austin (TX - USA) in Fall 1993 and in Spring 1994.

 

Education

  • Laurea Degree (M. Sc.) in Electrical Engineering, Politecnico di Milano (Italy), 1987. Final grade 100/100. MS Thesis on: “Theorical and numerical study of shallow waters fludodynamic models”, Advisor: Prof. G. Prouse, Politecnico di Milano. Co-Advisor Prof. L. Gotusso, Politecnico di Milano.

  • Ph. D. Degree in Computer Engineering, University of Brescia (Italy), 1999, Ph.D. Thesis title: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems”. Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano.

Research Activities

My research focuses on Computer Architecture and Electronic Design Automation, with particular emphasis on power-aware design, design space exploration of embedded architectures, adaptive design and monitoring of applications for many-core architectures, many-core architectures based on Networks-on-Chip, technology-aware many-core architectures and fault tolerant coding techniques. Highlights of my recent research can be found in the following five research papers:

  • ACM Trans. on Embedded Computing Systems 2013 [URL]

  • ACM Trans. on Embedded Computing Systems 2012 [URL]

  • IEEE Trans. on CAD 2009 [URL]

  • IEEE Trans. on Computers 2008 [URL]

  • IEEE Trans. on VLSI Systems 2006 [URL]

Research Projects and International Collaborations

My research activities have been carried out in collaboration with several international universities, research centers and industries (about 90 out of my 140 scientific publications include co-authors with different affiliations, 35 out of them with industrial co-authors, 106 co-authors overall). My research has been funded by several national and EU projects selected based on a competitive process. Since 2003 I was co-applicant and active participant of 7 European and 2 industrially funded projects (attracting around 3.5 M€ funding for POLIMI). Among them, I was:

  • Project Coordinator of the European Project FP7-2PARMA (2010-2013)  on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures";

  • Project Coordinator of the European Project FP7-MULTICUBE (2008-2010) on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications".

Since 1996 I have started a continuous research collaboration with STMicroelectronics and I was Principal Investigator of 2 industrial research projects funded by STMicroelectronics (2003-2008).

Scientific Outcomes

My scientific production consists of more than 140 scientific publications:

Based on Google Scholar (16/11/2014), my h-index is 25, my i10-index is 58 and my total number of citations is 2261 (my top ranked paper has been published in 1997 collecting up to 284 citations). 

 

Patents

Inventor/Co-inventor of 11 patent applications with Bull HN Information Systems and STMicroelectronics (7 out of 11 already granted).

  • Integrated CMOS static RAM, EU Patent # EP0578900 (B1) Granted 1997, DE Patent # DE69223046 (T2), Granted 1998. Applicant: Bul HN Information Systems (IT).

  • Digital information error correcting apparatus for single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC), US Patent # US5535227 (A) Granted 1996. EU Patent # EP0629051 (B1) Granted 1998, DE Patent # DE69317766 (T2) Granted 1998. Applicant: Bul HN Information Systems (IT).

  • Encoder/decoder architecture and related processing system, US Patent # US20020019896 (A1) Filed 2002. Encoder architecture for parallel busses, EU Patent # EP1150467 (A1) Filed 2001. Applicant: ST Microelectronics (IT).

  • Processor architecture US Patent # US6889317 (B2) Granted 2005. Processor architecture with variable-stage pipeline, EU Patent # EP1199629 (A1) Filed 2002. Applicant: ST Microelectronics (IT).

  • Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit. US Patent # US8185934 (B2), Granted 2012. EU Patent # EP2043324 (A1) Filed 2009. Applicant: STMicroelectronics Grenoble (F).

Link to: International Patents

Scientific Services

I am an active contributor to the scientific community and I regularly serve as Member (or Track Chair) of the Program Committee of several top-level conferences such as ICCAD, DAC, DATE, NOCS, HPCA, MICRO, ASAP, FPL. I was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. I was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). I have also organized several international workshops as Program or General Chair. I was Guest Co-Editor of two special issues on journals and Associate Editor of MICPRO Journal Embedded Hardware Design (Microprocessors and Microsystems), Elsevier. I am Senior Member of IEEE (since 2009) and Member of HiPEAC Network of Excellence.

ORGANIZING COMMITTEE MEMBER

  • Program Chair, FPL 2015, 25th International Conference on Field Programmable Logic and Applications, London (UK), Sept., 2015.
  • Subcommittee Chair, Embedded System Design, DAC 2015, 52nd ACM/IEEE Design Automation Conference, San Francisco CA, June 7-11, 2015.
  • Track Co-Chair, Architectural and Micro-architectural Design, DATE 2015, IEEE/ACM Design and Test in Europe Conference, Grenoble (France), March 9-13, 2015.
  • General Co-Chair, PARMA-DITAM Workshop 2015, co-located with HiPEAC 2015 Conference, Amsterdam (NL), Jan. 19-21,  2015.
  • Track Co-Chair, Design Methods and Tools, FPL 2014, 24th International Conference on Field Programmable Logic and Applications, Munich (Germany), Sept., 2014.
  • General Chair, PARMA-DITAM Workshop 2014, co-located with HiPEAC Conference 2014, Wien (A), Jan. 20, 2014.
  • Track Co-Chair, SoC Design and Interconnect, VLSI-SOC 2013, 21st IFIP/IEEE International Conference on Very Large Scale Integration, Istanbul (Turkey), October, 2013.
  • Workshops Co-Chair, FPL 2013, 23rd International Conference on Field Programmable Logic and Applications, Porto, Sept. 2-4, 2013.
  • General Co-Chair, DEPCP 2009-2013, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, 2009-2013.
  • General Co-Chair, Fall School on Programming Paradigms for Multi-core Embedded Systems, Freudenstadt – Lauterbad, Germany, October 2-5, 2012.
  • Program Co-Chair, ASAP 2012, 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors, Delft (NL), 9-11 July 2012.
  • Subcommitte Co-Chair, Embedded Systems Design Methodologies, DAC 2012, ACM/IEEE Design Automation Conference, San Francisco CA, 3-7 June 2012
  • Co-Organizer, RAPIDO Workshop 2010-2012 on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with HiPEAC Conference,  2010-2012.
  • Program Co-Chair, ARCS 2011, Architecture of Computing Systems Conference, Como (Italy), 22-25 Feb. 2011.
  • Top Picks 2010, Selection Committee Member, IEEE MICRO Special Issue on “Top Picks 2010 from Computer Architecture Conferences”, January/February 2011.
  • Program Co-Chair, SASP 2010, IEEE Symposium on Application Specific Processors (Co-located with ACM/IEEE Design Automation Conference), Anaheim, CA, June 13-18, 2010.
  • General Co-Chair, PARMA Workshop 2010 on Parallel Programming and Run-time Management Techniques for Many-core Architectures, co-located with ARCS 2010 - Architecture of Computing Systems Conference, Hannover (D), February 2010.
  • General Co-Chair, SASP 2009, IEEE Symposium on Application Specific Processors (Co-located with ACM/IEEE Design Automation Conference) San Francisco, CA, July 27-28, 2009.
  • Program Co-Chair, SAMOS IX Workshop on Systems, Architectures, Modeling and Simulation, Samos, Greece, July, 2009.
  • General Co-Chair, MICRO 2008, 41st Annual IEEE/ACM International Symposium on Microarchitecture, Como (Italy), 8-12 November 2008.
  • Publicity Chair, SASP 2008, IEEE Symposium on Application Specific Processors (Co-located with ACM/IEEE Design Automation Conference) Anaheim, CA, June 8-9, 2008.
  • Publicity Chair, WASP2007, Fifth Workshop on Application Specific Processors, 2007.

PROGRAM COMMITTEE MEMBER

  • IPDPS, IEEE International Parallel and Distributed Processing Symposium, 2015.

  • DAC, ACM/IEEE Design Automation Conference, 2011-2013, 2015.

  • DATE, IEEE/ACM Design and Test in Europe Conference, 2005-2015.

  • FPL, International Conference on Field Programmable Logic and Applications, 2013-2015.

  • ICCAD, IEEE/ACM International Conference on Computer-Aided Design, 2014.

  • NOCS, ACM/IEEE International Symposium on Networks-on-Chip, 2009-2014.

  • DSD, Euromicro Conference on Digital System Design, 2012- 2014.

  • ASAP, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2012-2014.

  • ARCS, Architecture of Computing Systems Conference, 2010-2014.

  • IC-SAMOS, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006-2014.

  • HPCC, IEEE International Conference on High Performance Computing and Communications, 2014.

  • ICPP, IEEE International Conference on Parallel Processing, 2011, 2013.

  • EUC 2013, IEEE/IFIP Int. Conf. on Embedded and Ubiquitous Computing, 2013.

  • MES 2013, International Workshop on Many-core Embedded  Systems.

  • VLSI-SOC, IFIP/IEEE International Conference on Very Large Scale Integration, 2008-2011, 2013.

  • HPCA-18, The 18th International Symposium on High Performance Computer Architecture, 2012.

  • IA^3, Workshop on irregular Applications: Architectures and Algorithms, 2011-2012.

  • CF, ACM International Conference on Computing Frontiers, 2009, 2012.

  • WRC, Workshop on Reconfigurable Computing, co-located with HiPEAC Conference, 2010-2012.

  • PDP, Euromicro International Conference on Parallel, Distributed and Network-Based Computing, 2012.

  • SASP, IEEE Symposium on Application Specific Processors, 2008-2011.

  • MICRO-43, 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010.

  • HiPEAC, International Conference on High-Performance Embedded Architectures and Compilers, 2010.

  • ICS, the 20th ACM International Conference on Supercomputing, 2006.

  • WASP, Workshop on Application Specific Processors, 2004-2007.

Evaluator of Research Projects for the European Commission:

  • Independent Expert Reviewer, ARTEMIS JU Project 295440 PaPP (Portable and Predictable Performance on heterogeneous embedded many-cores), 2013-2015.

  • Independent Expert Reviewer, European Project FP7-288570 ParaPhrase (Parallel Patterns for Adaptive Heterogeneous Multicore Systems), 2012-2014.

  • Independent Expert Reviewer, European Project FP7-248976-REFLECT (Rendering FPGAs to Multi-Core Embedded Computing), 2010-2012.

  • Independent Expert Reviewer to evaluate proposals submitted to the "Future and Emerging Technologies" programme (EC FET-Open) on FP7-ICT-2009, 2010-2013.

  • Independent Expert Reviewer to participate to the on-site Evaluation Panel for the EC "Future and Emerging Technologies" programme (EC FET-Open) on FP7-ICT-2009 Batch 13, June 2012.

  • Independent Expert Reviewer, Network-of-Excellence Project FP6-IST-4408 HiPEAC (High-Performance Embedded Architectures and Compilers), 2005-2008.

  • Independent Expert Reviewer to participate to the on-site Evaluation Panel for the EU IV Call IST (Information Society Technology) - FP6 (6th Framework Programme) on NanoelectronicsApril 2005.

Evaluator of Research Projects for Various Science Foundations:

  • Expert Reviewer, Programme Blanc International Edition 2010,  ANR (Agence Nationale de la Recherche), France, 2010.

  • Chair of the Review Panel, Academy of Finland, Research Council for Natural Sciences and Engineering, 2009.

  • Member of the Review Panel, Academy of Finland, Research Council for Natural Sciences and Engineering, 2008.

  • Primary Evaluator, INRIA (French National Institute for Computer Science,- France), 2007.

Recent Invited Talks, Seminars and Panels

  • October 8th, 2014, "Managing Adaptability in Heterogeneous Architectures through Performance Monitoring and Prediction", Invited Talk at the Thematic Section on Heterogeneous System Tools for Simulation, Debugging, Performance Modeling and Resource Management, HiPEAC Computing System Week, Athens, Host: Prof. Georgios Goumas, National Technical University of Athens. SLIDES

  • May 15th, 2014, "Managing Adaptability in Dynamically Reconfigurable Architectures through Performance Monitoring and Prediction", Invited Talk at the Thematic Section on Reconfigurable Architectures, HiPEAC Computing System Week, Barcelona, Host: Prof. Georgi Gaydadjiev, Chalmers University of Technology.

  • September 4th, 2013, Panel Moderator on: “EU Horizon 2020 on Reconfigurable Computing” Invited Speakers: Dr. Panos Tsarchopoulos, Future and Emerging Technologies, EU Project Officer; Dr. Georgi Kuzmanov, ARTEMIS Joint Undertaking, EU Programme Officer; Held at FPL2013, 23rd International Conference on Field Programmable Logic and Applications, Porto.

  • June 8th, 2012, “Automatic Design Space Exploration for Multi-core Architectures”, Seminar at Intel Labs, Santa Clara (USA), Host: Dr. Akhilesh Kumar, Intel.

  • April 25th, 2012. "Design-time support for run-time management of embedded multiprocessor architectures",  Invited Talk at the Thematic Section on Design and runtime management of reconfigurable systems, HiPEAC Computing System Week, Goteborg, Host: Prof. Georgi Gaydadjiev, Chalmers University of Technology.

  • February 7th, 2012, "Design Space Exploration and Run-time Resource Management for Multi-core Architectures", Seminar at the University of Texas at Austin (USA), Electrical and Computer Engineering, Computer Architecture Seminar Series, Austin, Host: Prof. Yale Patt, University of Texas at Austin. SLIDES

  • September 7th, 2011, "2PARMA Project" Invited Talk at FPL2011 European Project Workshop, Chania, Crete. Organizer. Prof. Joao Cardoso, Univ. of Porto.

  • April 7th, 2011, "2PARMA Project: PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures", Invited Talk at HIPEAC Cluster Meeting on Multi-core Architectures, 2011 Chamonix, Host: Prof. Per Stenström, Chalmers University of Technology. SLIDES

  • November 24th, 2010, "Automatic Design Space Exploration for Chip Multi-processors", Invited Talk at the Workshop on  Challenges in Embedded System Design: Involvement of SMEs in Designing Complex Systems (CMM 2010), University of Lugano, Switzerland, Workshop Organizers: Prof. G. De Micheli (EPFL) and Prof. M. Sami (USI-Politecnico di Milano).  SLIDES

  • July 6th, 2010, "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", Talk at the Research Projects Workshop at ISVLSI 2010: IEEE Computer Society Annual Symposium on VLSI, July 5-7, 2010, Lixouri Kefalonia. SLIDES

  • June 18th, 2010, Seminar at the Dept. of Computer Science & Engineering, University of California, Riverside, CA, USA,  "Automatic Design Space Exploration for Chip-Multi Processors" Host: Prof. Walid Najjar, University of California Riverside. SLIDES

  • June 17th, 2010, Seminar at the Dept. of Computer Science & Engineering, University of California, Irvine, CA, USA, "Automatic Design Space Exploration for Chip-Multiprocessors", Host: Prof. Alexander V. Veidenbaum, University of California Irvine. SLIDES

  • March 23rd, 2010,  Seminar at Delft Technical University, Computer Engineering Colloquium Series, Title: "A Design Space Exploration Framework for Run-Time Resource Management on Multi-Core Architectures"   Host: Prof. Koen Bertels, Delft Technical University. (Slides).

  • December 17, 2009, Seminar at NEC Laboratories America, Inc., Princeton Campus, Princeton (NJ - USA), Title: "Automatic Design Space Exploration for Chip-Multi Processors". Host: Dr. Marcello Lajolo, NEC Laboratories America.

  • December 16, 2009, Seminar at Princeton University, Department of Electrical Engineering, Computer Engineering Seminar, Title: "Automatic Design Space Exploration for Chip-Multi Processors", Host: Prof. Ruby Lee, Princeton University. (Announcement).

  • July 29th, 2009, Seminar at HP Labs, Palo Alto, Title: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs", Host: Dr. Matteo Monchiero, HP Labs, Palo Alto.

  • May 14th,2009,  Seminar at Delft Technical University, Computer Engineering Colloquium Series, Title: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space Exploration for CMPs" Host: Dr. Koen Bertels, Delft Technical University. (Slides).

Academic Services

I have balanced my effort in teaching at Undergraduate and M.Sc. level. I annually teach basic courses on Computer Architectures and Operating Systems and M.Sc. courses on Advanced Computer Architectures. I enjoy teaching and I have an extensive English-speaking teaching experience in a multi-cultural environment at Como Campus of Politecnico di Milano and more recently at Università della Svizzera Italiana (USI). My services for the last five years (2011-2015):

  • Advanced Computer Architectures (5 Credits), Master of Science, Computer Engineering, Politecnico di Milano, Como Campus (Course completely offered in English); Spring 2015; Spring 2014; Spring 2013; Spring 2012; Spring 2011;

  • Advanced Computer Architectures (5 Credits), Master of Science, Computer Engineering, Politecnico di Milano, Milano Leonardo Campus. (Course completely offered in English) Spring 2015; (in Italian) Fall 2013;

  • Computer Architectures and Operating Systems (I Module) (5 Credits), Undergraduate Programme, Computer Engineering, Politecnico di Milano, Como Campus. (in Italian) Fall 2013; Fall 2012;

  • Advanced Computer Architectures (3 Credits), Master of Science, Embedded System Design, Università della Svizzera Italiana, Lugano (Course completely offered in English). Fall 2012;

  • Computer Architectures and Operating Systems (10 Credits), Undergraduate Programme, Computer Engineering, Politecnico di Milano, Como Campus. (in Italian) Fall 2011; Fall 2010;

I am an active contributor to the organisation of teaching activities and tracks in Computer Engineering at POLIMI, mainly at Como Campus, where where I have had several responsibilities and I was participating to a number of committees:

  • Chair, Committee on Undergraduate Study Plans in Computer Engineering, Politecnico di Milano, Como Campus, 2002-Present.

  • Chair, Committee on Undergraduate Transfers in Computer Engineering, Politecnico di Milano, Como Campus, 2003-Present.

  • Member, Committee on Graduate Admissions in Computer Engineering, Politecnico di Milano, Como Campus, 2003-Present.

  • Member, Committee on Undergraduate Studies in Computer Engineering, Politecnico di Milano, Como Campus, 2003-Present.

I was advisor of 60+ M.Sc. students and advisor/co-advisor of 11 Ph.D. students. Currently, I am advisor of 3 Ph.D. students and my research staff is composed of two faculty members and two Post-doc researchers.

 

Ph.D. STUDENTS SUPERVISION


1

VITTORIO ZACCARIA, Ph. D. 2002, Politecnico di Milano. Currently Assistant Professor at Politecnico di Milano, DEIB. First employment: STMicroelectronics. Ph.D. thesis on: "Power exploration methodologies for VLIW-based systems". Advisor: prof. M. Sami. Co-Advisors: prof. D. Sciuto, Dr. C. Silvano.


2

GIANLUCA PALERMO, Ph.D. 2006, Politecnico di Milano. Currently Assistant Professor at Politecnico di Milano, DEIB. First employment: Post-Doc at Politecnico di Milano. Ph.D. thesis on: "Design Methodologies for Embedded Architectures based on Network on-Chip". Advisor: prof. C. Silvano.


3

GIOVANNI BELTRAME, Ph.D. 2006, Politecnico di Milano. Currently Assistant Professor at École Polytechnique de Montréal. First employment: European Space Agency (NL). Ph.D. thesis on “Modeling, Simulating, Analysis and Optimization of Multi-Processor System-on-Chip Platforms”. Advisor: prof. D. Sciuto. Co-Advisor: prof. C. Silvano.


4

MATTEO MONCHIERO, Ph.D. 2007, Politecnico di Milano. Currently Senior Research Scientist, Intel Labs at Santa Clara (CA, US). First employment: HP Labs in Palo Alto, Exascale Computing Lab. Ph.D. Thesis on: “Power/performance analysis and optimization of multicore architectures”. Advisor: prof. C. Silvano.


5

ORESTE VILLA, Ph.D. 2008, Politecnico di Milano.  Currently Senior Research Scientist at NVIDIA (CA, USA). First employment: Pacific Northwest National Lab, Richland, WA (USA), Ph.D. Thesis: “Designing and Programming Multi-core Architectures”. Advisor: prof. C. Silvano.


6

GIOVANNI MARIANI, Ph.D. 2011, Università della Svizzera Italiana (CH). Currently Post-Doctoral Researcher at ASTRON & IBM Center of Exascale Technology (NL). First employment: ALaRI-USI (CH) and TU Delft (NL). Ph.D. Thesis: "A Design Space Exploration Methodology Supporting Run-time Resource Management for Multi-Core Architectures". Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano.


7

LEANDRO FIORIN, Ph.D. 2012, Università della Svizzera Italiana (CH). Currently Post-Doctoral Researcher at ASTRON & IBM Center of Exascale Technology (NL). First employment: ALaRI-USI (CH). Ph.D. Thesis: "High level services for Networks-on-Chip”. Advisor: prof. M. Sami, Co-Advisor: prof. C. Silvano. 


8

EDOARDO PAONE, Ph. D. student at Politecnico di Milano, DEIB, XXVII cycle. Ph.D. Thesis: "Design Space Exploration of OpenCL Applications on Heterogeneous Parallel Platform”. Ph.D. defense expected Dec. 2014. Advisor: prof. C. Silvano.


9

IOANNIS STAMELAKOS, Ph. D. student at Politecnico di Milano, DEIB, XXVIII cycle. Ph.D. Thesis: “Technology-Aware Many-core Architecture Design”. Ph.D. defense expected 2016. Advisor: prof. C. Silvano. Co-advisor: prof. G. Palermo.


10

AMIR HOSSEIN ASHOURI
, Ph. D. student at Politecnico di Milano, DEIB, XXVIII cycle. Ph.D. Thesis: “Compiler/Architecture Co-exploration of Customized VLIW Architectures”. Ph.D. defense expected 2016. Advisor: prof. C. Silvano.
 

11

DAVIDE GADIOLI, Ph. D. student at Politecnico di Milano, DEIB, XXVII cycle. Ph.D. Thesis: Application Auto-Tuning and Run-Time Resource Management for Adaptive OpenCL Applications”.Ph.D. defense expected 2017.  Advisor: prof. C. Silvano. Co-advisor: prof. G. Palermo.

RESEARCH Visitors

  • Sotorios Xydis, Ph. D. from Technical University of Athens, Post-Doc at DEI, Politecnico di Milano (From Nov. 2011 to July 2013).

  • Arpad Gellért, Ph. D., Assistant Professor, “Lucian Blaga” University of Sibiu, Romania, Visiting Researcher, Spring 2009.

  • Caroline Concatto, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 15-01-10 to 15-04-10 , FP7 HiPEAC NoE Collaboration Grant.

  • Debora Matos, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.

  • Anelise Kologeski, Ph. D. student at Universidade Federal do Rio Grande do Sul, Instituto de Informática, Departamento de Informática Aplicada, Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. Visiting student from 02-02-11 al 02-05-11, FP7 HiPEAC NoE Collaboration Grant.