Link to CV (July 2014)
Current Position and Academic Career
I am currently Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), System Architectures Group. In December 2013, I have received the Scientific National Qualification in Italy as Full Professor in sector 09/H1 Information Processing Systems and in sector 01/B1 Informatics (as defined in DD222 of July 20, 2012). From 2006, I am also collaborating with ALaRI-Advanced Learning and Research Institute, part of the Faculty of Informatics of the Università della Svizzera Italiana (CH). From 2000 to 2002, I was Assistant Professor in Computer Science at University of Milan, Department of Computer Science. From 1999 to 2000, I was Post-Doctoral Researcher at Politecnico di Milano, mainly working on the research project: “Power estimation methodologies for VLIW architectures”, in collaboration with STMicroelectronics. From 1998 to 1999, I was Post-Doctoral Researcher in the Electronic Design Automation Area at CEFRIEL (Center for the Research and the Education in Information Engineering) in Milan. From March 1996 to October 1998, I was Ph.D. Student at Università degli Studi di Brescia (Italy). I have received the Ph. D. Degree in Computer Engineering on March 1999 discussing my thesis titled: “Power Estimation and Optimization Methodologies for Digital Circuits and Systems”. (Advisor: Prof. P. Gubian, Università degli Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).
From May 1987 to February 1996, I was with the R&D Laboratories of Group Bull (also known as Bull HN Information Systems), Pregnana Milanese (Italy), where I held the position of Design Engineer up to March 1993 and Senior Design Engineer up to February 1996. During this period, I was also Visiting Engineer at Bull R&D Labs, Billerica (MA - USA) in Fall 1988 and in Spring 1989. I also was Visiting Engineer at VLSI Technology Inc., Munich (Germany) in February-March 1990, and at VLSI Technology Inc. in S. José (CA-USA) in April 1990. From 1992, I was part of the Bull-IBM (Austin-US) design team for the design of the first multiprocessor system based on IBM PowerPC processor architecture. These shared-memory multiprocessor systems have been fully designed in the Bull R&D Labs in Italy and then commercialized as Bull Escala UNIX Servers and as IBM RS/6000 Symmetric Multiprocessor Servers. During this project, I was Visiting Engineer at IBM Somerset Design Center, Austin (TX - USA) in Fall 1993 and in Spring 1994.
My research focuses on Computer Architecture and Electronic Design Automation, with particular emphasis on power-aware design and design space exploration of embedded architectures, adaptive design and monitoring of applications for many-core architectures, many-core architectures based on Networks-on-Chip, technology-aware many-core architectures and fault tolerant coding techniques. Highlights of my recent research can be found in the following five research papers: ACM Trans. on Embedded Computing Systems 2013 [J2], ACM Trans. on Embedded Computing Systems 2012 [J5], IEEE Trans. on CAD 2009 [J8], IEEE Trans. on Computers 2008 [J9], IEEE Trans. on VLSI Systems 2006 [J13].
Research Projects and International Collaborations
My research activities have been carried out in collaboration with several international universities, research centers and industries (about 90 out of my 140 scientific publications include co-authors with different affiliations, 35 out of them with industrial co-authors, 106 co-authors overall). My research has been funded by several national and EU projects selected based on a competitive process. Since 2003 I was co-applicant and active participant of 7 European and 2 industrially funded projects (attracting around 3.5 M€ funding for POLIMI). Among them, I was Project Coordinator of two European projects: FP7-2PARMA (2010-2013) on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures" and previously FP7-MULTICUBE (2008-2010) on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications". Since 1996 I have started a continuous research collaboration with STMicroelectronics and I was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008).
My scientific production consists of more than 140 scientific publications:
- Co-author of 25 top-ranked journal publications (including 14 IEEE/ACM Transactions: 5 IEEE Trans. on VLSI Systems, 4 IEEE Trans. on CAD, 3 ACM Trans. on Embedded Computing Systems, 1 IEEE Trans. on Computers, 1 IEEE Trans. on Information Theory);
- Co-author of 13 chapters in scientific books;
- Co-author of more than 90 scientific publications on peer-reviewed conferences/workshops including 31 top-level conferences (15 DATE, 8 CODES-ISSS, 3 ASP-DAC, 2 DAC, 2 CASES and 1 ICCAD) collecting one Best Paper Award, one HiPEAC paper award and one of the most influential papers published at DATE conference in the decade 1998-2008;
- Co-author of the scientific book: “Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems”, Kluwer Academic Publisher (2003);
- Co-author of the academic textbook (in Italian): “Progettazione Digitale” (Logic Design), McGraw-Hill (2002, 2007);
- Co-editor of 2 scientific books: “Low-Power Networks-on-Chip”, Springer (2010) and “Multi-objective design space exploration of multiprocessor SoC architectures”, Springer (2011);
- Inventor/Co-inventor of 11 patent applications with Group Bull or STMicroelectronics (7 out of 11 already granted).
Based on Google Scholar (31/7/2014), my h-index is 25, my i10-index is 55 and my total number of citations is 2182 (my top ranked paper has been published in 1997 collecting up to 284 citations).
I am an active contributor to the scientific community and I regularly serve as Member (or Track Chair) of the Program Committee of several top-level conferences such as DAC, DATE, NOCS, HPCA, MICRO, ASAP, FPL. I was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. I was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). I have also organized 12 international workshops as Program or General Chair. I was Guest Co-Editor of two special issues on journals and Subject Area Editor of the Journal of System Architecture (Elsevier). I am Senior Member of IEEE (since 2009) and Member of HiPEAC Network of Excellence.
Evaluator of Research Projects for Various Science Foundations
I have been invited by the European Commission as Independent Expert to review several projects such as ARTEMIS JU Project 295440 PaPP (Portable and Predictable Performance on heterogeneous embedded many-cores), the FP7 STREP Project 288570 ParaPhrase (Parallel Patterns for Adaptive Heterogeneous Multicore Systems) and the FP7 STREP project 248976-REFLECT (Rendering FPGAs to Multi-Core Embedded Computing). From 2010 to 2012, she has been called from the European Commission as Independent Expert to evaluate proposals submitted to the EC "Future and Emerging Technologies" programme (EC FET-Open) on FP7-ICT-2009 Information and Communication Technologies. In 2010, she has been called as Reviewer of research proposals submitted to Programme Blanc International Edition 2010, ANR (Agence Nationale de la Recherche), France. From 2005 to 2008, she has been called from the European Commission as Independent Expert to review the Network-of-Excellence project FP6 - IST-4408 HiPEAC (High-Performance Embedded Architectures and Compilers). In April 2005, she has been called from the European Commission as Independent Expert to evaluate project proposals submitted to the IV Call IST (Information Society Technology) - FP6 (6th Framework Programme) on Nanoelectronics. In 2007, she has been called as Primary Evaluator for research projects at INRIA (French National Institute for Computer Science,- France). In 2008 she has been invited as Member of the Review Panel for Computer Science, Academy of Finland, Research Council for Natural Sciences and Engineering. In 2009 she has been invited as Chair of the same review panel.
Recent Invited Talks, Seminars and Panels
I have balanced my effort in teaching at Undergraduate and M.Sc. level. I annually teach basic courses on Computer Architectures and Operating Systems and M.Sc. courses on Advanced Computer Architectures. I enjoy teaching and I have an extensive English-speaking teaching experience in a multi-cultural environment at Como Campus of Politecnico di Milano and more recently at Università della Svizzera Italiana (USI). I am an active contributor to the organisation of teaching activities and tracks in Computer Engineering at POLIMI, mainly at Como Campus, where I am responsible for the Committee for the evaluation of undergrate study plans and I am participating to the Committee on teaching, the Committee on graduate admissions and the Committee on undergraduate transfers. I was advisor of 60+ M.Sc. students and advisor/co-advisor of 7 Ph.D. students. Currently, I am advisor of 3 Ph.D. students and my research staff is composed of two faculty members and two Post-doc researchers.
Ph.D. STUDENTS SUPERVISION: