The main topics for thesis works focuses on the areas of Computer Architectures and Computer Aided Design Methodologies, with particular emphasis on the following two current research topics:

  • Design Space Exploration of Multi/Many-Core Architectures
    The aim of the research is to investigate on power/performance tradeoffs in parallel on-chip architectures. The exploration techniques are based on multi-objective optimization algorithms and energy/delay estimation metrics. The basic idea is to provide an automatic Design Space Exploration methodology for the analysis of system characteristics and the selection of the most appropriate architectural solution to satisfy system requirements mainly in terms of performance and power consumption. The primary goal of the research was to define an automatic multi-objective DSE framework (namely MULTICUBE Explorer) to be used at design-time to find the best power/performance trade-offs while meeting system-level constraints and speeding up the exploration process. A set of heuristic optimization algorithms have been defined to reduce the exploration time, while a set of response surface modeling techniques have been defined to further speed up the process. Based on the results of the design-time multi-objective exploration, the research also defined a methodology to be used at run-time to optimize the allocation and scheduling of different application tasks. So far, the proposed methodology has been applied to several application domains to demonstrate their applicability and benefits in industrial contexts.

  • Network-on-Chip Architectures
    Given the increasing complexity of Multiprocessor System-on-Chip (MPSoC) designs, the current trends on on-chip communication architectures are converging towards the Network-on-Chip (NoC) approach representing a high bandwidth and low energy solution. Using the NoC-based design approach has several other advantages, such as scalability, reliability, IP reusability and separation of IP design from on-chip communication design and interfacing. NoC design represents a new paradigm to design MPSoC shifting the design methodologies from computation-based to communication-based. To address these NoC research challenges, my research is focusing on the topic of low-power NoC for embedded architectures, covering power and energy aware design and techniques from several perspectives and abstraction levels. We first developed PIRATE, a modular and flexible framework for power/performance exploration of Network-on-Chip architectures. The framework has been used for the exploration of distributed shared memory architectures based on NoC. Then, synchronization techniques for shared memory multi-core architectures based on Network-on-Chip have been proposed. Our research is also addressing the problems of the application mapping optimization and topology customization for the industrial STNoC architecture. Finally, we started investigating about security aspects in NoCs and adding high level services on top of the standard communication services usually provided by an interconnection network.

Some of the research topics can be carried out in collaboration with the Advanced System Technology -- STMicroelectronics, Agrate B. (MI)