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CRISTINA SILVANO

 

Cristina Silvano, named IEEE Fellow

Cristina Silvano has been named an IEEE Fellow. The IEEE Board of Directors, at its November 2016 meeting, elevated Cristina Silvano to IEEE Fellow, effective 1 January 2017. She has been recognized "for contributions to energy-efficient computer architectures". The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. The total number selected in any one year cannot exceed the 0.1% of the total voting membership. IEEE Fellow is the highest grade of membership and is recognized by the technical and scientific community as a prestigious honor and an important career achievement.

 

The ANTAREX research project, coordinated by Cristina Silvano from Politecnico di Milano, wins a 3 million euro grant in the European H2020 Future and Emerging Technologies programme on High Performance Computing. The project involves leading academic and industrial partners as well as CINECA, the Italian Tier-0 supercomputing centre and IT4i, the Czech Tier-1 supercomputing center. Being one of the nineteen research projects in FET-HPC-2014, ANTAREX brings the partners on the forefront of the European research in High Performance Computing. The main goal of the ANTAREX project is to provide a breakthrough approach to express by a Domain Specific Language the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing systems up to the Exascale level. The Consortium also includes three top-ranked academic partners (ETH Zurich, University of Porto, INRIA). Industrial partners include one of the leading biopharmaceutical companies in Europe (Dompé) and the top European navigation software company (Sygic).  The 3-year project started in September 2015.

The ANTAREX group photo at the Kick-off Meeting held in September 2015 at CINECA (Italy).

 

Near Threshold Computing. Technology, Methods and Applications, Editors: Michael Huebner, Cristina Silvano. Springer, 1st ed. 2016. Pre-print Front Matter PDF
This book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage. Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips. 
One selected chapter from this book: Ioannis Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano, "Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees", pp. 35-53. Pre-print Chapter Proof PDF

 

My keynote at EUC2015/CSE2015 in Porto (Portugal):

  • October 21st, 2015, "Design Space Exploration and Application Autotuning for Runtime Adaptivity in Multicore Architectures" Keynote Speaker at the 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC2015) / 18th IEEE International Conference on Computational Science and Engineering (CSE2015), Porto (Portugal),   SLIDES

My keynote at EUC2015 / CSE2015 , Porto (Portugal), October 21st, 2015

Program Committees I was recently involved in:

  • Chair of Track D8 on "Architectural and Microarchitectural Design" at  DATE 2017 IEEE/ACM Design and Test in Europe Conference, Lausanne (Swtizerland), March 27-31, 2017.
  • General Co-Chair, PARMA-DITAM Workshop 2017, co-located with HiPEAC 2017 Conference, Stockholm (Sweden), Jan. 25,  2017.
  • Track Chair, Hardware for Embedded Systems, ICCAD2016, The IEEE/ACM International Conference on Computer-Aided Design 2016, Austin, Texas, USA, November 7-10, 2016.
  • Local Organizer of HiPEAC Computing System Week,   held at in September 21-23 at Politecnico di Milano (Italy).
  • Program Chair at FPL 2015, 25th International Conference on Field Programmable Logic and Applications, London (UK), September, 2015.

FPL2015 Opening Session at the Royal Institution, London, September 2nd, 2015

About my research group:

  • Dr. Giovanni Mariani, formerly Post-Doctoral Researcher in my group at Politecnico di Milano, is now Post-Doctoral Researcher at IBM Research, ASTRON & IBM Center for Exascale Technology, the Nederlands.

  • Amir H. Ashouri, Ph.D. student in my group at Politecnico di Milano, DEIB, XXVIII cycle. Ph.D. Thesis on “Compiler Autotuning using Machine Learning Techniques”. Ph.D. defense in Dec. 2016.

  • Ioannis Stamelakos, Ph.D. student in my group at Politecnico di Milano, DEIB, XXVIII cycle. Ph.D. Thesis on “Near-Threshold Computing with Performance Guarantees for Manycore Architectures”. Ph.D. defense in Dec. 2016.