Embedded Systems 1 (Politecnico di Milano - Campus MI Leonardo - AA 2017/2018)

This section reports all the material and the information related to the laboratory and exercises for the Embedded Systems I course at Politecnico di Milano.
The professor in charge for the course is Prof. William Fornaciari and you can reach his webpage HERE.
Available projects will be presented during classes (LINK to ES1 Projects).

Schedule Hours Topic Material
October 24, 2017 3 Course Introduction & On-chip Bus & NoCs Intro, Bus, Bus Exercises
October 31, 2017 3 On-chip networks (NoCs) NoC, NoC Exercises
November 7, 2017 3 Cycle Accurate Simulation and gem5 gem5,
Install gem5 on Debian
[OracleVM with gem5]
November 23, 2017 3 Hardware Description Languages (HDLs) for Design RTL Design
November 30, 2017 3 Hardware Description Languages (HDLs) for Verification RTL Verification
December 1, 2017 2 Project Presentation (for Embedded Systems) ES1 Projects
December 5, 2017 3 SystemVerilog: Vivado + Exercises Vivado Design Suite - HLx Editions - 2017.2
vivado-logic-simulation_UG900_2017.3[link]
Simple Design and Testbench
December 6, 2017 2 Past Written Exams: Solved Exercises Dec_22_2016 [Q2.tb, Q2.circ_buffer]
Feb_28_2017 [Q2.uart_tb, Q2.uart]
Sept_5_2017 [sol]
December 19, 2017 2 Written Exam Scores
Solution Testbench
Solution Dut if parallel input
Solution Dut if serial input 1 bit per clock cycle
January 22, 2018 2 Written Exam Scores , Solution
Febrary 13, 2018 2 Written Exam Scores , Solution
June 26, 2018 2 Written Exam Scores , written exam , Q2 solution
July 19, 2018 2 Written Exam Scores , written exam , Testbench using Verilog 2001
Sept 05, 2018 2 Written Exam Scores , written exam , Testbench
, module

TOOLS, MATERIAL AND BOOK REFERENCES FOR THE COURSE
(NOTE: when REQUIRED tag is used it means the resource is mandatory to pass the written exam)

  • Bus-based Architectures
    • Book (REQUIRED) "Principles and Practices of Interconnection Networks", William Dally and Brian Towles. Morgan Kaufmann Publishers Inc., 2003. (Chapters 22)
    • Book"On-Chip Communication Architectures: System on Chip Interconnect", Sudeep Pasricha, Nikil Dutt. Morgan Kaufmann, 28/lug/2010. (Chapters 1,2)
  • Networks-on-Chip
    • Book (REQUIRED) "Designing network on-chip architectures in the nanoscale era", Jose Flich, Davide Bertozzi. 2011. (Chapters 1,2,3)
    • Book "Principles and Practices of Interconnection Networks", William Dally and Brian Towles. Morgan Kaufmann Publishers Inc., 2003. (Overview)
  • Hardware Description Language (HDL) (the subset of the specification discussed during classes is REQUIRED)
    • LRM Verilog 2001 Specification [link]
    • Article "I’m Still In Love With My X! (but, do I want my X to be an op timist, a pessimist, or eliminated?)", S. Sutherland, 2013. [link]
    • Article "Verilog 2001 Reference Guide", Sutherland, 2001. [link]
    • Article "Correct methods for Adding Delays to Verilog Behavioral Models", Clifford E. Cummings, HDLCON 1999. [link]
    • Book "FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version", Pong P. Chu, 2008. [link]

  • Additional Material
    • Low Power: Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi, "Low Power Methodology Manual: For System-on-Chip Design", Springer 2008
    • GEM5: www.m5sim.org/
    • LTSPICE: http://www.linear.com/designtools/software/
    • PTM models: http://ptm.asu.edu/ (to be used with LTSPICE)

© 2016 Davide Zoni